E2K: added initial support of MCST Elbrus 2000 CPU architecture

e2k (Elbrus 2000) - this is VLIW/EPIC architecture, like Intel Itanium (IA-64) architecture. Ref: https://en.wikipedia.org/wiki/Elbrus_2000 Signed-off-by: r-a-sattarov <r.a.sattarov@yandex.ru>
AcademySoftwareFoundation · Nov 23, 2020 · f04fcdd · f04fcdd
1 parent fb6a093
commit f04fcdd
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Showing 3 changed files with 55 additions and 9 deletions.
diff --git a/src/lib/OpenEXR/ImfFastHuf.cpp b/src/lib/OpenEXR/ImfFastHuf.cpp
@@ -316,15 +316,15 @@ FastHufDecoder::~FastHufDecoder()
 bool
 FastHufDecoder::enabled()
 {
-    #if defined(__INTEL_COMPILER) || defined(__GNUC__)  
+    #if defined(__INTEL_COMPILER) || defined(__GNUC__)
 
         //
         // Enabled for ICC, GCC:
         //       __i386__   -> x86
         //       __x86_64__ -> 64-bit x86
-        //
+        //       __e2k__    -> e2k (MCST Elbrus 2000)
 
-        #if defined (__i386__) || defined(__x86_64__)
+        #if defined (__i386__) || defined(__x86_64__) || defined(__e2k__)
             return true;
         #else
             return false;

diff --git a/src/lib/OpenEXR/ImfSimd.h b/src/lib/OpenEXR/ImfSimd.h
@@ -53,6 +53,27 @@
     #define IMF_HAVE_SSE4_1 1
 #endif
 
+// Compiler flags on e2k (MCST Elbrus 2000) architecture
+#if defined(__SSE3__) && defined(__e2k__)
+    #define IMF_HAVE_SSE3 1
+#endif
+
+#if defined(__SSSE3__) && defined(__e2k__)
+    #define IMF_HAVE_SSSE3 1
+#endif
+
+#if defined(__SSE4_2__) && defined(__e2k__)
+    #define IMF_HAVE_SSE4_2 1
+#endif
+
+#if defined(__AVX__) && defined(__e2k__)
+    #define IMF_HAVE_AVX 1
+#endif
+
+#if defined(__F16C__) && defined(__e2k__)
+    #define IMF_HAVE_F16C 1
+#endif
+
 extern "C"
 {
 #ifdef IMF_HAVE_SSE2

diff --git a/src/lib/OpenEXR/ImfSystemSpecific.cpp b/src/lib/OpenEXR/ImfSystemSpecific.cpp
@@ -40,27 +40,27 @@
 OPENEXR_IMF_INTERNAL_NAMESPACE_SOURCE_ENTER
 
 namespace {
-#if defined(IMF_HAVE_SSE2) &&  defined(__GNUC__)
+#if defined(IMF_HAVE_SSE2) &&  defined(__GNUC__) && !defined(__e2k__)
 
     // Helper functions for gcc + SSE enabled
     void cpuid(int n, int &eax, int &ebx, int &ecx, int &edx)
     {
         __asm__ __volatile__ (
             "cpuid"
-            : /* Output  */ "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx) 
+            : /* Output  */ "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
             : /* Input   */ "a"(n)
             : /* Clobber */);
     }
 
-#else // IMF_HAVE_SSE2 && __GNUC__
+#else // IMF_HAVE_SSE2 && __GNUC__ && !__e2k__
 
     // Helper functions for generic compiler - all disabled
     void cpuid(int n, int &eax, int &ebx, int &ecx, int &edx)
     {
         eax = ebx = ecx = edx = 0;
     }
 
-#endif // IMF_HAVE_SSE2 && __GNUC__
+#endif // IMF_HAVE_SSE2 && __GNUC__ && !__e2k__
 
 
 #ifdef IMF_HAVE_GCC_INLINEASM_X86
@@ -69,7 +69,7 @@ namespace {
     {
         __asm__ __volatile__ (
             "xgetbv"
-            : /* Output  */ "=a"(eax), "=d"(edx) 
+            : /* Output  */ "=a"(eax), "=d"(edx)
             : /* Input   */ "c"(n)
             : /* Clobber */);
     }
@@ -83,7 +83,7 @@ namespace {
 
 #endif //  IMF_HAVE_GCC_INLINEASM_X86
 
-} // namespace 
+} // namespace
 
 CpuId::CpuId():
     sse2(false), 
@@ -94,6 +94,30 @@ CpuId::CpuId():
     avx(false), 
     f16c(false)
 {
+#if defined(__e2k__) // e2k - MCST Elbrus 2000 architecture
+    // Use IMF_HAVE definitions to determine e2k CPU features
+#   if defined(IMF_HAVE_SSE2)
+        sse2 = true;
+#   endif
+#   if defined(IMF_HAVE_SSE3)
+        sse3 = true;
+#   endif
+#   if defined(IMF_HAVE_SSSE3)
+        ssse3 = true;
+#   endif
+#   if defined(IMF_HAVE_SSE4_1)
+        sse4_1 = true;
+#   endif
+#   if defined(IMF_HAVE_SSE4_2)
+        sse4_2 = true;
+#   endif
+#   if defined(IMF_HAVE_AVX)
+        avx = true;
+#   endif
+#   if defined(IMF_HAVE_F16C)
+        f16c = true;
+#   endif
+#else // x86/x86_64
     bool osxsave = false;
     int  max     = 0;
     int  eax, ebx, ecx, edx;
@@ -125,6 +149,7 @@ CpuId::CpuId():
             }
         }
     }
+#endif
 }
 
 OPENEXR_IMF_INTERNAL_NAMESPACE_SOURCE_EXIT