Team Members: Bijesh Subedi Aayush Gupta Kishor Subedi Anurag Kumar Yadav Sushan Dhakal

What is this repository ?

This repository consists of source code for a MIPS processor simulator. It supports single cycle processor with typical 5 stages(IF, ID, EX, MEM, WB) with one instruction per cycle.( Part 1 ) and a pipelined processor(with 5 instructions per cycle (in part 2 of the project). Cache_branch implements the cache in our C processor.

How to run?