VLSI-VHDL-Programs

This repo contains the VHDL Programs that I have completed in my M.Sc SEM-III using Xilinx ISE Design Suite

1. A 4 bit adder with structural model
2. Full adder with structural model
3. Full adder with behavioural model
4. Ripple carry adder
5. A 4 bit subtractor
6. Full subtractor
7. A 4 bit multiplier
8. A 4x4 bit multiplier
9. Comprator 3 bit
10. 4 Bit up counter with reset
11. 16 bit up counter with reset
12. Alternate Up/Down counter with reset
13. 4 Bit down counter

Each program has been written in file with .v extension. For example "1. Adder_4_Bit_Structural_Model" requires the following:

        Adder_1_Bit.v     // simple 1 bit adder file
        Adder_4_Bit.v     // 4 bit adder file that uses the 1 bit adders as a unit
        Adder_4_Bit_Testbench.v //Testbench file used to define possible cases to test the program against that