[AMD] Reland instruction scheduling hint changes #4940
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This reverts commit 93de426.
Replaced temlate-based impl. of `rewindUnaryOps` in `SchedInstructions.cpp` using regular for-loops. The new impl. is more robust and can handle other unary ops automatically.
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third_party/amd/lib/TritonAMDGPUTransforms/StreamPipelineV2.cpp
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* add a test for the presence of OpIdx attribute
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The extra check tests whether the data are loaded from HBM using `buffer_load` instructions. The CKV3 scheduling is skipped if the check fails.
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This commit relands #4819
with the following fixes:
rewindUnaryOpsto use regular for-loops. The new way is more robust and can handle other unary ops automatically.instr.sched.barriersusing the ones fromrocdldialect from the MLIR upstream