#
zynq-7000
Here are 5 public repositories matching this topic...
Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.
fpga
verilog
vivado
prefix-tree
adder
xilinx-fpga
xilinx-vivado
zynq-7000
han-carlson
brent-kung
kogge-stone-adder
ladner-fischer
carry-look-ahead-adder
ripple-carry-adder
carry-save-adder
prefix-adder
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Updated
Apr 13, 2021 - Verilog
Global Dark Mode for ALL apps on ANY platforms.
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Updated
Oct 3, 2023 - Verilog
Dual-Mode PSK Transceiver on SDR With FPGA
synchronization
fpga
zynq
amd
verilog
xilinx
sdr
vivado
transceiver
software-defined-radio
psk
demodulation
modulation
qpsk
bpsk
zynq-7000
costas-loop
zynq-7020
gardner
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Updated
Jan 17, 2024 - Verilog
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