vhdl
Here are 104 public repositories matching this topic...
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
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Jun 20, 2024 - Verilog
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
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Aug 12, 2017 - Verilog
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
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Aug 27, 2023 - Verilog
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
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Aug 13, 2023 - Verilog
This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…
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Mar 30, 2022 - Verilog
Hardware Formal Verification
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Aug 10, 2020 - Verilog
Projects and labs from the courses dictated in https://www.coursera.org/specializations/fpga-design. Projects are sometimes simulated, and implemented in either a MAX10-Lite or an Arrow MAX1000 board.-
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Mar 22, 2021 - Verilog
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
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Jan 16, 2023 - Verilog
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
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Oct 30, 2017 - Verilog
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
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Sep 10, 2023 - Verilog
Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.
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Apr 12, 2020 - Verilog
This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..
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Mar 16, 2020 - Verilog
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