✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
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Updated
Sep 29, 2024 - Python
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
Cross EDA Abstraction and Automation
An approachable testing framework for digital hardware
An abstract language model of VHDL written in Python.
This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
A flexible and scalable development platform for modern FPGA projects.
A simple python script to generate a VHDL testbench template given an entity-architecture declaration passed as argument(s) as a file(s)
An abstraction library for interfacing EDA tools
Configurable AES-GCM IP (128, 192, 256 bits)
GitHub Action to install Orbit
Gather version information and export as any programming language source file for inclusion into compilation.
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