vhdl
Here are 110 public repositories matching this topic...
A simple python script to generate a VHDL testbench template given an entity-architecture declaration passed as argument(s) as a file(s)
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Sep 17, 2024 - Python
GitHub Action to install Orbit
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Jul 25, 2024 - Python
A simple VHDL test bench generator (for combinational logic) written in Python
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May 13, 2020 - Python
VHDL / System Verilog to Verilog converter, based on Yosys and the plugins ghdl-yosys-plugin and synlig.
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Feb 4, 2024 - Python
This is a python script that automatically generates testbench templates for Verilog and VHDL source files. It parses the provided HDL source file for a module's name, parameters, and ports and then writes a testbench template for that module. This can be used to automate and streamline the process of setting up simulations for your HDL modules.…
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Jul 3, 2021 - Python
create a VHDL instantiation template from Verilog source
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Feb 26, 2024 - Python
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May 15, 2024 - Python
A python script that generates VHDL files describing steps for a modular reduction in hardware
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Feb 15, 2020 - Python
SublimeLinter plugin for linting VHDL with Modelsim vcom
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Dec 21, 2017 - Python
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