Labs and project for the EE102 Introduction to Digital Circuit Design course.
-
Updated
Sep 28, 2024 - HTML
Labs and project for the EE102 Introduction to Digital Circuit Design course.
🛜 Golay Code error correction scheme for LoRaWAN systems was described. GFSK modulation (and demodulation) scheme was implemented in an AWGN channel. Encoding and decoding this model using the binary Golay Codes was done which gives a lower BER. The BER curves have been plotted for varying SNR.
This is a 4 bit AOU (Arithmetic Operator Unit) which was implemented by Spartan 6 FPGA. It can perform all the basic mathematical operations in a single time.
Designed a Single Cycle 6-stage pipelined Processor which can execute 26 different instructions and implemented it in code in VHDL
A Cellular Neural Network SoC implementation with learning algorithm on VHDL. (Digilent Atlys Board)
Flappy Bird on FPGA using VHDL
Codes for the courses gone through in college for B.Tech CSE
CSE460 - VLSI Design
Programming on Mimas V2 Spartan 6 FPGA Development Board (Spartan XC6SLX9 in CSG324 package) using VHDL to make a VGA Driver. Tic-Tac-Toe game is demonstrated.
CPRE 381 Project 2 Pipelined Processor - Both hardware and software
Add a description, image, and links to the vhdl topic page so that developers can more easily learn about it.
To associate your repository with the vhdl topic, visit your repo's landing page and select "manage topics."