vhdl
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All digital lowpas delta-sigma modulator (+digital up-converter) tune to fmax = 9 MHz
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Jan 15, 2018 - HTML
Programming on Mimas V2 Spartan 6 FPGA Development Board (Spartan XC6SLX9 in CSG324 package) using VHDL to make a VGA Driver. Tic-Tac-Toe game is demonstrated.
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Jan 5, 2023 - HTML
📚Repositório da Disciplina INE5406 - Sistemas Digitais
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Jun 21, 2018 - HTML
Designed a Single Cycle 6-stage pipelined Processor which can execute 26 different instructions and implemented it in code in VHDL
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Jul 21, 2023 - HTML
A Simple ALU design using Structural style on VHDL
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Jun 1, 2018 - HTML
Diseño de sistemas Digitales con lattice Diamond y FPGA
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Jan 27, 2018 - HTML
🛜 Golay Code error correction scheme for LoRaWAN systems was described. GFSK modulation (and demodulation) scheme was implemented in an AWGN channel. Encoding and decoding this model using the binary Golay Codes was done which gives a lower BER. The BER curves have been plotted for varying SNR.
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Sep 5, 2023 - HTML
This is a 4 bit AOU (Arithmetic Operator Unit) which was implemented by Spartan 6 FPGA. It can perform all the basic mathematical operations in a single time.
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Sep 1, 2023 - HTML
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Nov 8, 2017 - HTML
CPRE 381 Project 2 Pipelined Processor - Both hardware and software
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Oct 4, 2022 - HTML
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