verilog
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OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Oct 1, 2024 - Verilog
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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Oct 1, 2024 - Verilog
learn the combinational and sequential logic circuit.
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Oct 1, 2024 - SystemVerilog
Verilator open-source SystemVerilog simulator and lint system
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Oct 1, 2024 - C++
Veryl: A Modern Hardware Description Language
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Oct 1, 2024 - Rust
XLS: Accelerated HW Synthesis
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Oct 1, 2024 - C++
Test suite designed to check compliance with the SystemVerilog standard.
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Oct 1, 2024 - SystemVerilog
This project automates process of creating a PYNQ Z2 Overlay in Vivado, generates a custom Juypter Notebook template and uploads to a target PYNQ FPGA.
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Sep 30, 2024 - Python
Digital logic design tool and simulator
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Sep 30, 2024 - Java
Traces, schematics, and general infos about custom chips reverse-engineered from silicon
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Sep 30, 2024 - Verilog
BDD Gherkin implementation in native SystemVerilog, based on UVM.
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Oct 1, 2024 - SystemVerilog
HDL libraries and projects
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Oct 1, 2024 - Verilog
RISC-V Linux SoC, marchID: 0x2b
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Sep 30, 2024 - C
Python Templated Verilog
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Sep 30, 2024 - Rust
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