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The Rocks Community profile and public information
Multicycle processor in Chisel3
Updated
May 30, 2022
Verilog
My interests and some collaborations
Test enviroment to connect jigsaw devices w/ Ibex core in CHISEL & compile the design w/ CIRCT IR to analyze the dumped SV
Updated
Oct 4, 2022
SystemVerilog
Open source flow for generating bitstreams from Chisel code
Updated
Oct 6, 2023
Makefile
A Chisel HDL template using Scala Bleep build tool
Updated
Aug 2, 2023
Scala
Porting all Ethernaut challenges to Foundry
Updated
Mar 13, 2024
Solidity
<Digital Design with Chisel> 中译版 <Chisel 数字电路设计>
The practice of learning the Chisel bootcamp from GitHub repo whose website is below:
Updated
Jan 8, 2024
Jupyter Notebook
Przykład użycia generatora Chisel
Updated
Dec 3, 2017
Scala
RTL related scripts to ASIC/FPGA
Updated
Jun 13, 2022
Python
A template Chisel project for the DE1SOC FPGA board
Updated
Feb 13, 2020
Scala
Runs a Chisel server on Heroku platform. Requires `container` stack.
Updated
May 29, 2021
Dockerfile
This project helps developers create FPGA based systems with zephyr rtos.The goal of this project is to build Zephyr RTOS in a way similar to Xilinx's PetaLinux workflow.
Updated
Feb 13, 2023
Verilog
Updated
May 10, 2023
Shell
Updated
Apr 25, 2024
Scala
Updated
Oct 14, 2017
Java
Collection of utilities to simplify FPGA accelerator design
Updated
Apr 12, 2019
Scala
Updated
Dec 1, 2021
Scala
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