ReLM is the soft-core multiprocessor technology based on the unique memory architecture, enabling users to build a high-performance microcontroller on a relatively small FPGA board.
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Updated
Aug 25, 2024 - Python
ReLM is the soft-core multiprocessor technology based on the unique memory architecture, enabling users to build a high-performance microcontroller on a relatively small FPGA board.
Team 21 - Mini-Project
This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.
透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。
Research & Development FPGA projects for different boards
Flappy Bird on FPGA using VHDL
📌 The idea of this project is to build a system that uses the existing lights to detect the location of a user within an indoor environment. For this, we can use Visible Light Communication (VLC) technology. The basic concept is to have four LEDs transmitting their IDs one after the other at fixed intervals.
Laboratório de Arquitetura de Sistemas Digitais, ministrado pelo professor Rafael Bezerra Correia Lima. Foram desenvolvidos 8 requisitos de hardware, 1 requisito de software e 1 projeto de disciplina que totalizam 10 Sprints. A arquitetura de sistemas implementada é baseada em MIPS 8 bits, e desenvolvidos e testados na FGPA Ciclone II EP2C35F672C6
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
Implementation of an Edge Detection Filter Using the Avalon Interface
Graph Processing Framework that supports || OpenMP || CAPI
FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA
A scalable and freely configurable function generator in VHDL
Verilog based HDMI for Cyclone V or Altera series
UART Receiver and Transmitter using Terasic DE-10 Standard FPGA
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
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