EV21 RISC Processor Design
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Updated
Jul 8, 2021 - Verilog
EV21 RISC Processor Design
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
Lab exercises on digital circuit design using Altera Quartus 9.1sp2
Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board
An 8-bit processor in VHDL based on a simple instruction set
A scalable and freely configurable function generator in VHDL
These labs were conducted during our Digital systems elective course were we were instructed to build Verilog code for specific logic design and verify it on Quartus modalism and on the FPGA. Skills developed: writing Verilog code structurally and behaviorally, testing, simulation, writing test benches and using the FPGA
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
Digital clock in VHDL, on Altera Cyclone IV FPGA Board A-C4E6. This work was presented on PLP discipline during electrical engineer course at Mackenzie Presbyterian University.
Research & Development FPGA projects for different boards
UART Receiver and Transmitter using Terasic DE-10 Standard FPGA
Laboratório de Arquitetura de Sistemas Digitais, ministrado pelo professor Rafael Bezerra Correia Lima. Foram desenvolvidos 8 requisitos de hardware, 1 requisito de software e 1 projeto de disciplina que totalizam 10 Sprints. A arquitetura de sistemas implementada é baseada em MIPS 8 bits, e desenvolvidos e testados na FGPA Ciclone II EP2C35F672C6
Graph Processing Framework that supports || OpenMP || CAPI
💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board
Flappy Bird on FPGA using VHDL
Hardware Praktikum at Uni Freiburg
Verilog based HDMI for Cyclone V or Altera series
ReLM is the soft-core multiprocessor technology based on the unique memory architecture, enabling users to build a high-performance microcontroller on a relatively small FPGA board.
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