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05_counter.jed
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05_counter.jed
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Note: The first character in the file is 0x02(Start Transmission)*
N Comment Lines just have to start with an N, all lines end with a *
N: This file was based on a file written by Minipro open source software v0.4dev*
N: The information in this file is compiled from the following sources and experimentation*
N: JEDEC File Format Specification*
N: http://www.pldtool.com/pdf/fmt_jedec.pdf *
N: Lattice Original GAL16v8 Datasheet *
N: http://ee-classes.usc.edu/ee459/library/datasheets/16v8.pdf *
N: ATMEL/Microchip ATF16v8B Datasheet *
N: http://ww1.microchip.com/downloads/en/devicedoc/atmel-0364-pld-atf16v8b-8bq-8bql-datasheet.pdf *
N: Minipro software gitlab site *
N: https://gitlab.com/DavidGriffith/minipro/ *
N: Peepaw McDonald's video Generic Array Logic Hand Disassembly of the JEDEC File *
N: https://www.youtube.com/watch?v=h_d4npbKpdY *
N: FUNCTION *
N: This file uses the register mode to show how a simple binary counter could be implemented. *
N: If this were independent logic pieces the solution might be to feed outputs in to the clock to built a ripple counter. *
N: The 16V8 does not allow modifying the source of the clock so this circuit must look to the transition of the full 8-bit *
N: state. However each output only has 8 terms so there needs to be some optimizations to make it fit. *
N: +-------+ *
N: Clock -| 1 20|- Vcc *
N: /RESET -| 2 19|- Output7 (MSB) *
N: UNUSED -| 3 18|- Output6 *
N: UNUSED -| 4 17|- Output5 *
N: UNUSED -| 5 16|- Output4 *
N: UNUSED -| 6 15|- Output3 *
N: UNUSED -| 7 14|- Output2 *
N: UNUSED -| 8 13|- Output1 *
N: UNUSED -| 9 12|- Output0 (LSB) *
N: GND -|10 11|- /OE *
N: +-------+ *
N: | Prev State | Next State | *
N: |------------|------------| *
N: | 0000 0000 | 0000 0001 | *
N: | 0000 0001 | 0000 0010 | *
N: | 0000 0010 | 0000 0011 | *
N: . *
N: . *
N: . *
N: | 1111 1101 | 1111 1110 | *
N: | 1111 1110 | 1111 1111 | *
N: | 1111 1111 | 0000 0000 | *
N: Register Mode *
N: A = Pin 2 *
N: B = Pin 19 *
N: C = Pin 3 *
N: D = Pin 18 *
N: E = Pin 4 *
N: F = Pin 17 *
N: G = Pin 5 *
N: H = Pin 16 *
N: I = Pin 6 *
N: J = Pin 15 *
N: K = Pin 7 *
N: L = Pin 14 *
N: M = Pin 8 *
N: N = Pin 13 *
N: O = Pin 9 *
N: P = Pin 12 *
N: Pin1 : Clock *
N: Pin11: /OE *
N: Output0 (O0 or P) will toggle every clock so it is easy: *
N: O0 = /P *
N: O1 (aka N) needs to toggle every time O0 goes low. *
N: | 00 | 01 | *
N: | 01 | 10 | *
N: | 10 | 11 | *
N: | 11 | 00 | *
N: So for this we can just go the easy way and look what previous states cause *
N: the second bit to be high (01, 10) and encode both of them: *
N: O1 = /NP + N/P *
N: 02 (aka L) is next lets take a look at its cycle: *
N: | 000 | 001 | *
N: | 001 | 010 | *
N: | 010 | 011 | *
N: | 011 | 100 | *
N: | 100 | 101 | *
N: | 101 | 110 | *
N: | 110 | 111 | *
N: | 111 | 000 | *
N: There is a enough logic to encoded the previous states where O2 is high: *
N: 02 = /LNP + L/N/P + L/NP + LP/N *
N: *
N: However this can be reduced, as this Kaurnaugh Map shows: *
N: L\NP *
N: \ 00 01 11 10 *
N: 0|0 |0 |1 |0 | *
N: 1|1 |1 |0 |1 | *
N: *
N: 02 = /LNP + L/N + L/P *
N: *
N: The key from this statement is that the pattern reveals how the reduction *
N: can be generalized. *
N: A bit will be high if: *
N: 1) it was low and all less significant bits are high *
N: 2) or it was high and at least one less significant bit was low *
N: Using this pattern we can fill in the rest of the equations. *
N: 03 = /JLNP + J/L + J/N + J/P *
N: 04 = /HJLNP + H/J + H/L + H/N + H/P *
N: 05 = /FHJLNP + F/H + F/J + F/L + F/N + F/P *
N: 06 = /DFHJLNP + D/F + D/H + D/J + D/L + D/N + D/P *
N: 07 = /BDFHJLNP + B/D + B/F + B/H + B/J + B/L + B/N + B/P *
N: 07 only has 8 terms so it will fit in the 16V8. There is actually enough *
N: logic space to add one more feature a reset pin that will clear the counter *
N: bits. *
N: In this file it is implemented using active low. The 16V8 floats inputs *
N: high, so the reset will be disabled. It is best practice to explicitly tie *
N: the signal high though. *
N: This design uses pin 2 (aka A) to do this, but it could fairly easily be *
N: changed to one of the other unused inputs or made active high if needed. *
N: The reset is actually implemented by making every term rely on pin2 (A) *
N: being high. This modifies every AND term, but doesn't OR in anything new *
N: preventing an increase in need for logic resources. *
N: Because the device is using register mode pin11 must be tied low to enable *
N: the output.*
N: (D) sets the device type*
Device: ATF16V8B*
N (QP) 20 Pins in the ATF16V8B*
QP20*
N: (QF) 2194 Fuses in the ATF16V8B*
QF2194*
N: (F) Default Fuse Setting 0*
F0*
N: (G) Security Fuse set this to 1 to turn on DRM (Boo!)*
G0*
N: (L) These are the Actual fuse setting Starting with the address and then the bits in order *
N: 0=connected, 1=disconnect *
N: The connected signals in each row are ANDed together.*
N: Each block of 8 rows is then ORed together to get the input to the output logic specified by the Mode fuses.*
N: Unused OR gate inputs are usually set to all 0s to hold the unused input low*
N: 07 = A/BDFHJLNP + AB/D + AB/F + AB/H + AB/J + AB/L + AB/N + AB/P *
N: Block for PIN 19 *
N: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _*
N: AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPP*
L0000 01101101110111011101110111011101*
L0032 01011110111111111111111111111111*
L0064 01011111111011111111111111111111*
L0096 01011111111111101111111111111111*
L0128 01011111111111111110111111111111*
L0160 01011111111111111111111011111111*
L0192 01011111111111111111111111101111*
L0224 01011111111111111111111111111110*
N: 06 = A/DFHJLNP + AD/F + AD/H + AD/J + AD/L + AD/N + AD/P *
N: Block for PIN 18 *
N: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _*
N: AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPP*
L0256 00000000000000000000000000000000*
L0288 01111110110111011101110111011101*
L0320 01111101111011111111111111111111*
L0352 01111101111111101111111111111111*
L0384 01111101111111111110111111111111*
L0416 01111101111111111111111011111111*
L0448 01111101111111111111111111101111*
L0480 01111101111111111111111111111110*
N: 05 = A/FHJLNP + AF/H + AF/J + AF/L + AF/N + AF/P *
N: Block for PIN 17 *
N: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _*
N: AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPP*
L0512 00000000000000000000000000000000*
L0544 00000000000000000000000000000000*
L0576 01111111111011011101110111011101*
L0608 01111111110111101111111111111111*
L0640 01111111110111111110111111111111*
L0672 01111111110111111111111011111111*
L0704 01111111110111111111111111101111*
L0736 01111111110111111111111111111110*
N: 04 = A/HJLNP + AH/J + AH/L + AH/N + AH/P *
N: Block for PIN 16 *
N: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _*
N: AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPP*
L0768 00000000000000000000000000000000*
L0800 00000000000000000000000000000000*
L0832 00000000000000000000000000000000*
L0864 01111111111111101101110111011101*
L0896 01111111111111011110111111111111*
L0928 01111111111111011111111011111111*
L0960 01111111111111011111111111101111*
L0992 01111111111111011111111111111110*
N: 03 = A/JLNP + AJ/L + AJ/N + AJ/P *
N: Block for PIN 15 *
N: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _*
N: AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPP*
L1024 00000000000000000000000000000000*
L1056 00000000000000000000000000000000*
L1088 00000000000000000000000000000000*
L1120 00000000000000000000000000000000*
L1152 01111111111111111110110111011101*
L1184 01111111111111111101111011111111*
L1216 01111111111111111101111111101111*
L1248 01111111111111111101111111111110*
N: 02 = A/LNP + AL/N + AL/P *
N: Block for PIN 14 *
N: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _*
N: AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPP*
L1280 00000000000000000000000000000000*
L1312 00000000000000000000000000000000*
L1344 00000000000000000000000000000000*
L1376 00000000000000000000000000000000*
L1408 00000000000000000000000000000000*
L1440 01111111111111111111111011011101*
L1472 01111111111111111111110111101111*
L1504 01111111111111111111110111111110*
N: O1 = A/NP + AN/P *
N: Block for PIN 13 *
N: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _*
N: AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPP*
L1536 00000000000000000000000000000000*
L1568 00000000000000000000000000000000*
L1600 00000000000000000000000000000000*
L1632 00000000000000000000000000000000*
L1664 00000000000000000000000000000000*
L1696 00000000000000000000000000000000*
L1728 01111111111111111111111111101101*
L1760 01111111111111111111111111011110*
N: O0 = A/P *
N: Block for PIN 12 *
N: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _*
N: AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPP*
L1792 00000000000000000000000000000000*
L1824 00000000000000000000000000000000*
L1856 00000000000000000000000000000000*
L1888 00000000000000000000000000000000*
L1920 00000000000000000000000000000000*
L1952 00000000000000000000000000000000*
L1984 00000000000000000000000000000000*
L2016 01111111111111111111111111111110*
N: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _*
N: AABBCCDDEEFFGGHHIIJJKKLLMMNNOOPP*
N: XOR set to the the active state of each output (0=low, 1=high)*
N: 11111111*
N: 98765432*
L2048 11111111*
N: Signature*
L2056 0101010101010101010101010101010101010101010101010101010101010101*
N: AC1 sets whether the output pin is registered(0-output pin, 1-input pin)*
N: In register mode, registered outputs feedback the output whether enabled or not *
N: combinatorial outputs use the first logic line to control OE per pin *
N: 11111111*
N: 98765432*
L2120 00000000*
N: PTD for each input to the OR's from the fuse lines above this sets if they are (1-enabled, 0-disabled)*
L2128 1111111111111111111111111111111111111111111111111111111111111111*
N: SYN and AC0 Sets mode of chip*
N: 00 - Undefined *
N: 01 - Register Mode *
N: 10 - Simple Mode *
N: 11 - Complex Mode *
L2192 01*
N: (C) Checksum of the fuse (L & F) data. The minipro tool can ignore this and will actually tell you how to set it if you want to turn off the warning*
C8ba5*
N: The first character in the last line of the file is 0x03(End Transmission) followed by the file checksum lowercase hex*
N: minipro can ignore this and will actually tell you how to set it if you want to turn off the warning or release a file with an appropriate checksum*
cb94