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model.flow.rpt
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model.flow.rpt
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Flow report for model
Tue Dec 08 16:20:35 2020
Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+------------------------------------------+
; Flow Status ; Successful - Tue Dec 08 16:20:35 2020 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
; Revision Name ; model ;
; Top-level Entity Name ; model ;
; Family ; Cyclone III ;
; Met timing requirements ; N/A ;
; Total logic elements ; 322 / 5,136 ( 6 % ) ;
; Total combinational functions ; 313 / 5,136 ( 6 % ) ;
; Dedicated logic registers ; 120 / 5,136 ( 2 % ) ;
; Total registers ; 120 ;
; Total pins ; 70 / 183 ( 38 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 423,936 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
; Device ; EP3C5F256C6 ;
; Timing Models ; Final ;
+------------------------------------+------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/08/2020 16:20:07 ;
; Main task ; Compilation ;
; Revision Name ; model ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+-------------------------------+---------------+-------------+----------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+-------------------------------+---------------+-------------+----------------------+
; COMPILER_SIGNATURE_ID ; 1097497982274.160742280704436 ; -- ; -- ; -- ;
; CYCLONEII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
; EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ; Design Compiler ; <None> ; -- ; -- ;
; EDA_INPUT_DATA_FORMAT ; Edif ; -- ; -- ; eda_design_synthesis ;
; EDA_INPUT_VCC_NAME ; Vdd ; -- ; -- ; eda_design_synthesis ;
; EDA_LMF_FILE ; altsyn.lmf ; -- ; -- ; eda_design_synthesis ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_timing_analysis ;
; EDA_SIMULATION_TOOL ; Active-HDL (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; EDA_TIMING_ANALYSIS_TOOL ; PrimeTime (Verilog) ; <None> ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+-------------------------------+---------------+-------------+----------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:03 ; 1.0 ; 217 MB ; 00:00:03 ;
; Fitter ; 00:00:08 ; 1.0 ; 309 MB ; 00:00:07 ;
; Assembler ; 00:00:03 ; 1.0 ; 215 MB ; 00:00:03 ;
; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 245 MB ; 00:00:03 ;
; EDA Netlist Writer ; 00:00:03 ; 1.0 ; 180 MB ; 00:00:03 ;
; Total ; 00:00:21 ; -- ; -- ; 00:00:19 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+--------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; USER-PC ; Windows Vista ; 6.1 ; x86_64 ;
; Fitter ; USER-PC ; Windows Vista ; 6.1 ; x86_64 ;
; Assembler ; USER-PC ; Windows Vista ; 6.1 ; x86_64 ;
; TimeQuest Timing Analyzer ; USER-PC ; Windows Vista ; 6.1 ; x86_64 ;
; EDA Netlist Writer ; USER-PC ; Windows Vista ; 6.1 ; x86_64 ;
+---------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off model -c model
quartus_fit --read_settings_files=off --write_settings_files=off model -c model
quartus_asm --read_settings_files=off --write_settings_files=off model -c model
quartus_sta model -c model
quartus_eda --read_settings_files=off --write_settings_files=off model -c model