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minor rtl edits #948

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merged 6 commits into from
Jul 10, 2024
Merged

minor rtl edits #948

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7f17958
[rtl] add bus comments; remove PMP constraints
stnolting Jul 10, 2024
6f4393f
[rtl] top: remove PMP granularity constraints
stnolting Jul 10, 2024
b878b00
[rtl] pmp: remove granularity constraints
stnolting Jul 10, 2024
526397b
[rtl] io switch: add port defaults
stnolting Jul 10, 2024
2ac2f06
[vivado_ip] cleanup tcl script
stnolting Jul 10, 2024
b32225b
[changelog] add v1.10.1.2
stnolting Jul 10, 2024
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12

| Date | Version | Comment | Ticket |
|:----:|:-------:|:--------|:------:|
| 10.07.2024 | 1.10.1.2 | minor rtl edits and cleanups | [#948](https://github.com/stnolting/neorv32/pull/948) |
| 05.07.2024 | 1.10.1.1 | minor rtl cleanups and optimizations | [#941](https://github.com/stnolting/neorv32/pull/941) |
| 04.07.2024 | [**:rocket:1.10.1**](https://github.com/stnolting/neorv32/releases/tag/v1.10.1) | **New release** | |
| 04.07.2024 | 1.10.0.10 | :warning: rework GPTMRM and remove capture mode | [#939](https://github.com/stnolting/neorv32/pull/939) |
Expand Down
2 changes: 1 addition & 1 deletion rtl/core/neorv32_cpu_pmp.vhd
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Expand Up @@ -21,7 +21,7 @@ use neorv32.neorv32_package.all;
entity neorv32_cpu_pmp is
generic (
NUM_REGIONS : natural range 0 to 16; -- number of regions (0..16)
GRANULARITY : natural range 4 to natural'high; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
TOR_EN : boolean; -- implement TOR mode
NAP_EN : boolean -- implement NAPOT/NA4 modes
);
Expand Down
137 changes: 69 additions & 68 deletions rtl/core/neorv32_intercon.vhd
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Expand Up @@ -357,6 +357,7 @@ end neorv32_bus_gateway_rtl;
-- NEORV32 SoC - Processor Bus Infrastructure: IO Switch --
-- -------------------------------------------------------------------------------- --
-- Simple switch for accessing one out of several (IO) devices. --
-- Note: Enabled ports do not have to be contiguous. --
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --
Expand All @@ -376,76 +377,76 @@ entity neorv32_bus_io_switch is
generic (
DEV_SIZE : natural; -- size of a single IO device, has to be a power of two
-- device port enable and base address --
DEV_00_EN : boolean; DEV_00_BASE : std_ulogic_vector(31 downto 0);
DEV_01_EN : boolean; DEV_01_BASE : std_ulogic_vector(31 downto 0);
DEV_02_EN : boolean; DEV_02_BASE : std_ulogic_vector(31 downto 0);
DEV_03_EN : boolean; DEV_03_BASE : std_ulogic_vector(31 downto 0);
DEV_04_EN : boolean; DEV_04_BASE : std_ulogic_vector(31 downto 0);
DEV_05_EN : boolean; DEV_05_BASE : std_ulogic_vector(31 downto 0);
DEV_06_EN : boolean; DEV_06_BASE : std_ulogic_vector(31 downto 0);
DEV_07_EN : boolean; DEV_07_BASE : std_ulogic_vector(31 downto 0);
DEV_08_EN : boolean; DEV_08_BASE : std_ulogic_vector(31 downto 0);
DEV_09_EN : boolean; DEV_09_BASE : std_ulogic_vector(31 downto 0);
DEV_10_EN : boolean; DEV_10_BASE : std_ulogic_vector(31 downto 0);
DEV_11_EN : boolean; DEV_11_BASE : std_ulogic_vector(31 downto 0);
DEV_12_EN : boolean; DEV_12_BASE : std_ulogic_vector(31 downto 0);
DEV_13_EN : boolean; DEV_13_BASE : std_ulogic_vector(31 downto 0);
DEV_14_EN : boolean; DEV_14_BASE : std_ulogic_vector(31 downto 0);
DEV_15_EN : boolean; DEV_15_BASE : std_ulogic_vector(31 downto 0);
DEV_16_EN : boolean; DEV_16_BASE : std_ulogic_vector(31 downto 0);
DEV_17_EN : boolean; DEV_17_BASE : std_ulogic_vector(31 downto 0);
DEV_18_EN : boolean; DEV_18_BASE : std_ulogic_vector(31 downto 0);
DEV_19_EN : boolean; DEV_19_BASE : std_ulogic_vector(31 downto 0);
DEV_20_EN : boolean; DEV_20_BASE : std_ulogic_vector(31 downto 0);
DEV_21_EN : boolean; DEV_21_BASE : std_ulogic_vector(31 downto 0);
DEV_22_EN : boolean; DEV_22_BASE : std_ulogic_vector(31 downto 0);
DEV_23_EN : boolean; DEV_23_BASE : std_ulogic_vector(31 downto 0);
DEV_24_EN : boolean; DEV_24_BASE : std_ulogic_vector(31 downto 0);
DEV_25_EN : boolean; DEV_25_BASE : std_ulogic_vector(31 downto 0);
DEV_26_EN : boolean; DEV_26_BASE : std_ulogic_vector(31 downto 0);
DEV_27_EN : boolean; DEV_27_BASE : std_ulogic_vector(31 downto 0);
DEV_28_EN : boolean; DEV_28_BASE : std_ulogic_vector(31 downto 0);
DEV_29_EN : boolean; DEV_29_BASE : std_ulogic_vector(31 downto 0);
DEV_30_EN : boolean; DEV_30_BASE : std_ulogic_vector(31 downto 0);
DEV_31_EN : boolean; DEV_31_BASE : std_ulogic_vector(31 downto 0)
DEV_00_EN : boolean := false; DEV_00_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_01_EN : boolean := false; DEV_01_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_02_EN : boolean := false; DEV_02_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_03_EN : boolean := false; DEV_03_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_04_EN : boolean := false; DEV_04_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_05_EN : boolean := false; DEV_05_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_06_EN : boolean := false; DEV_06_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_07_EN : boolean := false; DEV_07_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_08_EN : boolean := false; DEV_08_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_09_EN : boolean := false; DEV_09_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_10_EN : boolean := false; DEV_10_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_11_EN : boolean := false; DEV_11_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_12_EN : boolean := false; DEV_12_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_13_EN : boolean := false; DEV_13_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_14_EN : boolean := false; DEV_14_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_15_EN : boolean := false; DEV_15_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_16_EN : boolean := false; DEV_16_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_17_EN : boolean := false; DEV_17_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_18_EN : boolean := false; DEV_18_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_19_EN : boolean := false; DEV_19_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_20_EN : boolean := false; DEV_20_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_21_EN : boolean := false; DEV_21_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_22_EN : boolean := false; DEV_22_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_23_EN : boolean := false; DEV_23_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_24_EN : boolean := false; DEV_24_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_25_EN : boolean := false; DEV_25_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_26_EN : boolean := false; DEV_26_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_27_EN : boolean := false; DEV_27_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_28_EN : boolean := false; DEV_28_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_29_EN : boolean := false; DEV_29_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_30_EN : boolean := false; DEV_30_BASE : std_ulogic_vector(31 downto 0) := (others => '-');
DEV_31_EN : boolean := false; DEV_31_BASE : std_ulogic_vector(31 downto 0) := (others => '-')
);
port (
-- host port --
main_req_i : in bus_req_t; -- host request
main_rsp_o : out bus_rsp_t; -- host response
-- device ports --
dev_00_req_o : out bus_req_t; dev_00_rsp_i : in bus_rsp_t;
dev_01_req_o : out bus_req_t; dev_01_rsp_i : in bus_rsp_t;
dev_02_req_o : out bus_req_t; dev_02_rsp_i : in bus_rsp_t;
dev_03_req_o : out bus_req_t; dev_03_rsp_i : in bus_rsp_t;
dev_04_req_o : out bus_req_t; dev_04_rsp_i : in bus_rsp_t;
dev_05_req_o : out bus_req_t; dev_05_rsp_i : in bus_rsp_t;
dev_06_req_o : out bus_req_t; dev_06_rsp_i : in bus_rsp_t;
dev_07_req_o : out bus_req_t; dev_07_rsp_i : in bus_rsp_t;
dev_08_req_o : out bus_req_t; dev_08_rsp_i : in bus_rsp_t;
dev_09_req_o : out bus_req_t; dev_09_rsp_i : in bus_rsp_t;
dev_10_req_o : out bus_req_t; dev_10_rsp_i : in bus_rsp_t;
dev_11_req_o : out bus_req_t; dev_11_rsp_i : in bus_rsp_t;
dev_12_req_o : out bus_req_t; dev_12_rsp_i : in bus_rsp_t;
dev_13_req_o : out bus_req_t; dev_13_rsp_i : in bus_rsp_t;
dev_14_req_o : out bus_req_t; dev_14_rsp_i : in bus_rsp_t;
dev_15_req_o : out bus_req_t; dev_15_rsp_i : in bus_rsp_t;
dev_16_req_o : out bus_req_t; dev_16_rsp_i : in bus_rsp_t;
dev_17_req_o : out bus_req_t; dev_17_rsp_i : in bus_rsp_t;
dev_18_req_o : out bus_req_t; dev_18_rsp_i : in bus_rsp_t;
dev_19_req_o : out bus_req_t; dev_19_rsp_i : in bus_rsp_t;
dev_20_req_o : out bus_req_t; dev_20_rsp_i : in bus_rsp_t;
dev_21_req_o : out bus_req_t; dev_21_rsp_i : in bus_rsp_t;
dev_22_req_o : out bus_req_t; dev_22_rsp_i : in bus_rsp_t;
dev_23_req_o : out bus_req_t; dev_23_rsp_i : in bus_rsp_t;
dev_24_req_o : out bus_req_t; dev_24_rsp_i : in bus_rsp_t;
dev_25_req_o : out bus_req_t; dev_25_rsp_i : in bus_rsp_t;
dev_26_req_o : out bus_req_t; dev_26_rsp_i : in bus_rsp_t;
dev_27_req_o : out bus_req_t; dev_27_rsp_i : in bus_rsp_t;
dev_28_req_o : out bus_req_t; dev_28_rsp_i : in bus_rsp_t;
dev_29_req_o : out bus_req_t; dev_29_rsp_i : in bus_rsp_t;
dev_30_req_o : out bus_req_t; dev_30_rsp_i : in bus_rsp_t;
dev_31_req_o : out bus_req_t; dev_31_rsp_i : in bus_rsp_t
dev_00_req_o : out bus_req_t; dev_00_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_01_req_o : out bus_req_t; dev_01_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_02_req_o : out bus_req_t; dev_02_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_03_req_o : out bus_req_t; dev_03_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_04_req_o : out bus_req_t; dev_04_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_05_req_o : out bus_req_t; dev_05_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_06_req_o : out bus_req_t; dev_06_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_07_req_o : out bus_req_t; dev_07_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_08_req_o : out bus_req_t; dev_08_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_09_req_o : out bus_req_t; dev_09_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_10_req_o : out bus_req_t; dev_10_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_11_req_o : out bus_req_t; dev_11_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_12_req_o : out bus_req_t; dev_12_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_13_req_o : out bus_req_t; dev_13_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_14_req_o : out bus_req_t; dev_14_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_15_req_o : out bus_req_t; dev_15_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_16_req_o : out bus_req_t; dev_16_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_17_req_o : out bus_req_t; dev_17_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_18_req_o : out bus_req_t; dev_18_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_19_req_o : out bus_req_t; dev_19_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_20_req_o : out bus_req_t; dev_20_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_21_req_o : out bus_req_t; dev_21_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_22_req_o : out bus_req_t; dev_22_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_23_req_o : out bus_req_t; dev_23_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_24_req_o : out bus_req_t; dev_24_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_25_req_o : out bus_req_t; dev_25_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_26_req_o : out bus_req_t; dev_26_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_27_req_o : out bus_req_t; dev_27_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_28_req_o : out bus_req_t; dev_28_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_29_req_o : out bus_req_t; dev_29_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_30_req_o : out bus_req_t; dev_30_rsp_i : in bus_rsp_t := rsp_terminate_c;
dev_31_req_o : out bus_req_t; dev_31_rsp_i : in bus_rsp_t := rsp_terminate_c
);
end neorv32_bus_io_switch;

Expand All @@ -454,9 +455,9 @@ architecture neorv32_bus_io_switch_rtl of neorv32_bus_io_switch is
-- module configuration --
constant num_devs_c : natural := 32; -- number of device ports

-- address bits for access decoding --
constant abb_lo_c : natural := index_size_f(DEV_SIZE); -- low address boundary bit
constant abb_hi_c : natural := (index_size_f(DEV_SIZE) + index_size_f(num_devs_c)) - 1; -- high address boundary bit
-- address bit boundaries for access decoding --
constant addr_lo_c : natural := index_size_f(DEV_SIZE); -- low address boundary bit
constant addr_hi_c : natural := (index_size_f(DEV_SIZE) + index_size_f(num_devs_c)) - 1; -- high address boundary bit

-- list of enabled device ports --
type dev_en_list_t is array (0 to num_devs_c-1) of boolean;
Expand Down Expand Up @@ -530,7 +531,7 @@ begin
bus_request: process(main_req_i)
begin
dev_req(i) <= main_req_i;
if (main_req_i.addr(abb_hi_c downto abb_lo_c) = dev_base_list_c(i)(abb_hi_c downto abb_lo_c)) then
if (main_req_i.addr(addr_hi_c downto addr_lo_c) = dev_base_list_c(i)(addr_hi_c downto addr_lo_c)) then
dev_req(i).stb <= main_req_i.stb; -- propagate transaction strobe if address match
else
dev_req(i).stb <= '0';
Expand Down
14 changes: 7 additions & 7 deletions rtl/core/neorv32_package.vhd
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Expand Up @@ -29,7 +29,7 @@ package neorv32_package is

-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100101"; -- hardware version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100102"; -- hardware version
constant archid_c : natural := 19; -- official RISC-V architecture ID
constant XLEN : natural := 32; -- native data path width

Expand Down Expand Up @@ -128,19 +128,19 @@ package neorv32_package is
addr : std_ulogic_vector(31 downto 0); -- access address
data : std_ulogic_vector(31 downto 0); -- write data
ben : std_ulogic_vector(3 downto 0); -- byte enable
stb : std_ulogic; -- request strobe (single-shot)
stb : std_ulogic; -- request strobe, single-shot
rw : std_ulogic; -- 0=read, 1=write
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
priv : std_ulogic; -- set if privileged (machine-mode) access
rvso : std_ulogic; -- set if reservation set operation (atomic LR/SC)
fence : std_ulogic; -- fence(.i) operation, independent of STB
fence : std_ulogic; -- set if fence(.i) operation, single-shot, independent of STB
end record;

-- bus response --
type bus_rsp_t is record
data : std_ulogic_vector(31 downto 0); -- read data
ack : std_ulogic; -- access acknowledge (single-shot)
err : std_ulogic; -- access error (single-shot)
data : std_ulogic_vector(31 downto 0); -- read data, valid if ack=1
ack : std_ulogic; -- access acknowledge, single-shot
err : std_ulogic; -- access error, single-shot
end record;

-- source (request) termination --
Expand Down Expand Up @@ -737,7 +737,7 @@ package neorv32_package is
REGFILE_HW_RST : boolean := false;
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural range 0 to 16 := 0;
PMP_MIN_GRANULARITY : natural range 4 to 2**30 := 4;
PMP_MIN_GRANULARITY : natural := 4;
PMP_TOR_MODE_EN : boolean := true;
PMP_NAP_MODE_EN : boolean := true;
-- Hardware Performance Monitors (HPM) --
Expand Down
2 changes: 1 addition & 1 deletion rtl/core/neorv32_top.vhd
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Expand Up @@ -54,7 +54,7 @@ entity neorv32_top is

-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural range 0 to 16 := 0; -- number of regions (0..16)
PMP_MIN_GRANULARITY : natural range 4 to 2**30 := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
PMP_TOR_MODE_EN : boolean := true; -- implement TOR mode
PMP_NAP_MODE_EN : boolean := true; -- implement NAPOT/NA4 modes

Expand Down
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