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⚠️ rename SPI & XIP module's top interface ports #504

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merged 7 commits into from
Feb 24, 2023
Merged

⚠️ rename SPI & XIP module's top interface ports #504

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15328dd
:warning: rename SPI & XIP top ports
stnolting Feb 24, 2023
c03b02d
[docs] rename XIP and SPI ports
stnolting Feb 24, 2023
5bd1206
[CHANGELOG] add v1.8.1.2
stnolting Feb 24, 2023
956ee32
[rtl/system_integration] typo fixes
stnolting Feb 24, 2023
49f4f7e
[rtl]system_integration] another typo fix...
stnolting Feb 24, 2023
6fa0d8d
[CHANGELOG] typo fix
stnolting Feb 24, 2023
e34e587
[rtl] restore original IMEM image (revert)
stnolting Feb 24, 2023
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -31,6 +31,7 @@ mimpid = 0x01040312 => Version 01.04.03.12 => v1.4.3.12

| Date (*dd.mm.yyyy*) | Version | Comment |
|:-------------------:|:-------:|:--------|
| 24.02.2023 | 1.8.1.2 | :warning: rename top interface signals of **XIP** and **SIP** modules; [#504](https://github.com/stnolting/neorv32/pull/504) |
| 23.02.2023 | 1.8.1.1 | CFS: add another 32 interface register (now having 64 memory-mapped registers for custom usage); [#503](https://github.com/stnolting/neorv32/pull/503) |
| 23.02.2023 | [**:rocket:1.8.1**](https://github.com/stnolting/neorv32/releases/tag/v1.8.1) | **New release** |
| 22.02.2023 | 1.8.0.10 | :warning: **remove stream link interface (SLINK)**; [#502](https://github.com/stnolting/neorv32/pull/502) |
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10 changes: 5 additions & 5 deletions docs/datasheet/soc.adoc
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Expand Up @@ -94,8 +94,8 @@ bits/channels are hardwired to zero.
4+^| **Execute In Place Interface (<<_execute_in_place_module_xip,**XIP**>>)**
| `xip_csn_o` | 1 | out | chi select, low-active
| `xip_clk_o` | 1 | out | serial clock
| `xip_sdi_i` | 1 | in | serial data input
| `xip_sdo_o` | 1 | out | serial data output
| `xip_dat_i` | 1 | in | serial data input
| `xip_dat_o` | 1 | out | serial data output
4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
| `gpio_o` | 64 | out | general purpose parallel output
| `gpio_i` | 64 | in | general purpose parallel input
Expand All @@ -110,9 +110,9 @@ bits/channels are hardwired to zero.
| `uart1_rts_o` | 1 | out | RX ready to receive new char
| `uart1_cts_i` | 1 | in | TX allowed to start sending
4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)**
| `spi_sck_o` | 1 | out | controller clock line
| `spi_sdo_o` | 1 | out | serial data output
| `spi_sdi_i` | 1 | in | serial data input
| `spi_clk_o` | 1 | out | controller clock line
| `spi_dat_o` | 1 | out | serial data output
| `spi_dat_i` | 1 | in | serial data input
| `spi_csn_o` | 8 | out | dedicated chip select (low-active)
4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
| `twi_sda_io` | 1 | inout | serial data line
Expand Down
8 changes: 4 additions & 4 deletions docs/datasheet/soc_spi.adoc
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Expand Up @@ -8,9 +8,9 @@
| Hardware source file(s): | neorv32_spi.vhd |
| Software driver file(s): | neorv32_spi.c |
| | neorv32_spi.h |
| Top entity port: | `spi_sck_o` | 1-bit serial clock output
| | `spi_sdo_o` | 1-bit serial data output
| | `spi_sdi_i` | 1-bit serial data input
| Top entity port: | `spi_clk_o` | 1-bit serial clock output
| | `spi_dat_o` | 1-bit serial data output
| | `spi_dat_i` | 1-bit serial data input
| | `spi_csn_i` | 8-bit dedicated chip select (low-active)
| Configuration generics: | _IO_SPI_EN_ | implement SPI controller when _true_
| | _IO_SPI_FIFO_ | data FIFO size, has to be zero or a power of two
Expand Down Expand Up @@ -90,7 +90,7 @@ image::SPI_timing_diagram2.wikimedia.png[]
| _SPI_CTRL_CPHA_ | `0` | `1` | `0` | `1`
|=======================

The SPI clock frequency (`spi_sck_o`) is programmed by the 3-bit _SPI_CTRL_PRSCx_ clock prescaler for a coarse selection
The SPI clock frequency (`spi_clk_o`) is programmed by the 3-bit _SPI_CTRL_PRSCx_ clock prescaler for a coarse selection
and a 4-bit clock divider _SPI_CTRL_CDIVx_ for a fine selection.

The following pre-scalers (_SPI_CTRL_PRSCx_) are available:
Expand Down
4 changes: 2 additions & 2 deletions docs/datasheet/soc_xip.adoc
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Expand Up @@ -10,8 +10,8 @@
| | neorv32_xip.h |
| Top entity port: | `xip_csn_o` | 1-bit chip select, low-active
| | `xip_clk_o` | 1-bit serial clock output
| | `xip_sdi_i` | 1-bit serial data input
| | `xip_sdo_o` | 1-bit serial data output
| | `xip_dat_i` | 1-bit serial data input
| | `xip_dat_o` | 1-bit serial data output
| Configuration generics: | _IO_XIP_EN_ | implement XIP module when _true_
| CPU interrupts: | none |
|=======================
Expand Down
2 changes: 1 addition & 1 deletion rtl/core/neorv32_application_image.vhd
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Expand Up @@ -2,7 +2,7 @@
-- Auto-generated memory initialization file (for APPLICATION) from source file <demo_blink_led/main.bin>
-- Size: 1076 bytes
-- MARCH: default
-- Built: 21.01.2023 15:20:33
-- Built: 24.02.2023 18:13:22

-- prototype defined in 'neorv32_package.vhd'
package body neorv32_application_image is
Expand Down
36 changes: 24 additions & 12 deletions rtl/core/neorv32_package.vhd
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Expand Up @@ -65,7 +65,7 @@ package neorv32_package is

-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080101"; -- NEORV32 version
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080102"; -- NEORV32 version
constant archid_c : natural := 19; -- official RISC-V architecture ID

-- Check if we're inside the Matrix -------------------------------------------------------
Expand Down Expand Up @@ -224,7 +224,19 @@ package neorv32_package is

-- reserved --
--constant reserved_base_c : std_ulogic_vector(31 downto 0) := x"ffffff00"; -- base address
--constant reserved_size_c : natural := 16*4; -- module's address space size in bytes
--constant reserved_size_c : natural := 2*4; -- module's address space size in bytes

-- reserved --
--constant reserved_base_c : std_ulogic_vector(31 downto 0) := x"ffffff08"; -- base address
--constant reserved_size_c : natural := 2*4; -- module's address space size in bytes

-- reserved --
--constant reserved_base_c : std_ulogic_vector(31 downto 0) := x"ffffff10"; -- base address
--constant reserved_size_c : natural := 4*4; -- module's address space size in bytes

-- reserved --
--constant reserved_base_c : std_ulogic_vector(31 downto 0) := x"ffffff20"; -- base address
--constant reserved_size_c : natural := 8*4; -- module's address space size in bytes

-- Execute In Place Module (XIP) --
constant xip_base_c : std_ulogic_vector(31 downto 0) := x"ffffff40"; -- base address
Expand Down Expand Up @@ -1057,8 +1069,8 @@ package neorv32_package is
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
xip_csn_o : out std_ulogic; -- chip-select, low-active
xip_clk_o : out std_ulogic; -- serial clock
xip_sdi_i : in std_ulogic := 'L'; -- device data input
xip_sdo_o : out std_ulogic; -- controller data output
xip_dat_i : in std_ulogic := 'L'; -- device data input
xip_dat_o : out std_ulogic; -- controller data output
-- GPIO (available if IO_GPIO_NUM > 0) --
gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input
Expand All @@ -1073,9 +1085,9 @@ package neorv32_package is
uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
spi_clk_o : out std_ulogic; -- SPI serial clock
spi_dat_o : out std_ulogic; -- controller data out, peripheral data in
spi_dat_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic; -- twi serial data line
Expand Down Expand Up @@ -1770,9 +1782,9 @@ package neorv32_package is
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- com lines --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
spi_clk_o : out std_ulogic; -- SPI serial clock
spi_dat_o : out std_ulogic; -- controller data out, peripheral data in
spi_dat_i : in std_ulogic; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
-- interrupt --
irq_o : out std_ulogic -- transmission done interrupt
Expand Down Expand Up @@ -2033,8 +2045,8 @@ package neorv32_package is
-- SPI device interface --
spi_csn_o : out std_ulogic; -- chip-select, low-active
spi_clk_o : out std_ulogic; -- serial clock
spi_data_i : in std_ulogic; -- device data output
spi_data_o : out std_ulogic -- controller data output
spi_dat_i : in std_ulogic; -- device data output
spi_dat_o : out std_ulogic -- controller data output
);
end component;

Expand Down
34 changes: 17 additions & 17 deletions rtl/core/neorv32_spi.vhd
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Expand Up @@ -7,7 +7,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -61,9 +61,9 @@ entity neorv32_spi is
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- com lines --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
spi_clk_o : out std_ulogic; -- SPI serial clock
spi_dat_o : out std_ulogic; -- controller data out, peripheral data in
spi_dat_i : in std_ulogic; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
-- interrupt --
irq_o : out std_ulogic -- transmission done interrupt
Expand Down Expand Up @@ -275,7 +275,7 @@ begin
tx_fifo_inst: neorv32_fifo
generic map (
FIFO_DEPTH => IO_SPI_FIFO, -- number of fifo entries; has to be a power of two; min 1
FIFO_WIDTH => 32, -- size of data elements in fifo (32-bit only for simulation)
FIFO_WIDTH => 32, -- size of data elements in fifo
FIFO_RSYNC => false, -- async read
FIFO_SAFE => true, -- safe access
FIFO_GATE => false -- no output gate required
Expand Down Expand Up @@ -312,7 +312,7 @@ begin
rx_fifo_inst: neorv32_fifo
generic map (
FIFO_DEPTH => IO_SPI_FIFO, -- number of fifo entries; has to be a power of two; min 1
FIFO_WIDTH => 32, -- size of data elements in fifo (32-bit only for simulation)
FIFO_WIDTH => 32, -- size of data elements in fifo
FIFO_RSYNC => false, -- async read
FIFO_SAFE => true, -- safe access
FIFO_GATE => false -- no output gate required
Expand Down Expand Up @@ -412,7 +412,7 @@ begin

when "100" => -- enabled but idle, waiting for new transmission trigger
-- ------------------------------------------------------------
spi_sck_o <= ctrl.cpol;
spi_clk_o <= ctrl.cpol;
rtx_engine.bitcnt <= (others => '0');
if (rtx_engine.start = '1') then -- trigger new transmission
rtx_engine.sreg <= tx_fifo.rdata;
Expand All @@ -423,16 +423,16 @@ begin
-- ------------------------------------------------------------
if (spi_clk_en = '1') then
if (ctrl.cpha = '1') then -- clock phase shift
spi_sck_o <= not ctrl.cpol;
spi_clk_o <= not ctrl.cpol;
end if;
rtx_engine.state(1 downto 0) <= "10";
end if;

when "110" => -- first half of bit transmission
-- ------------------------------------------------------------
if (spi_clk_en = '1') then
spi_sck_o <= not (ctrl.cpha xor ctrl.cpol);
rtx_engine.sdi_sync <= spi_sdi_i; -- sample data input
spi_clk_o <= not (ctrl.cpha xor ctrl.cpol);
rtx_engine.sdi_sync <= spi_dat_i; -- sample data input
rtx_engine.bitcnt <= std_ulogic_vector(unsigned(rtx_engine.bitcnt) + 1);
rtx_engine.state(1 downto 0) <= "11";
end if;
Expand All @@ -442,18 +442,18 @@ begin
if (spi_clk_en = '1') then
rtx_engine.sreg <= rtx_engine.sreg(30 downto 0) & rtx_engine.sdi_sync; -- shift and set output
if (rtx_engine.bitcnt(5 downto 3) = rtx_engine.bytecnt) then -- all bits transferred?
spi_sck_o <= ctrl.cpol;
spi_clk_o <= ctrl.cpol;
rtx_engine.done <= '1'; -- done!
rtx_engine.state(1 downto 0) <= "00"; -- transmission done
else
spi_sck_o <= ctrl.cpha xor ctrl.cpol;
spi_clk_o <= ctrl.cpha xor ctrl.cpol;
rtx_engine.state(1 downto 0) <= "10";
end if;
end if;

when others => -- "0--": SPI deactivated
-- ------------------------------------------------------------
spi_sck_o <= ctrl.cpol;
spi_clk_o <= ctrl.cpol;
rtx_engine.sreg <= (others => '0');
rtx_engine.state(1 downto 0) <= "00";

Expand All @@ -468,10 +468,10 @@ begin
data_size: process(ctrl, rtx_engine)
begin
case ctrl.rtx_size is
when "00" => rtx_engine.bytecnt <= "001"; spi_sdo_o <= rtx_engine.sreg(07); -- 8-bit mode
when "01" => rtx_engine.bytecnt <= "010"; spi_sdo_o <= rtx_engine.sreg(15); -- 16-bit mode
when "10" => rtx_engine.bytecnt <= "011"; spi_sdo_o <= rtx_engine.sreg(23); -- 24-bit mode
when others => rtx_engine.bytecnt <= "100"; spi_sdo_o <= rtx_engine.sreg(31); -- 32-bit mode
when "00" => rtx_engine.bytecnt <= "001"; spi_dat_o <= rtx_engine.sreg(07); -- 8-bit mode
when "01" => rtx_engine.bytecnt <= "010"; spi_dat_o <= rtx_engine.sreg(15); -- 16-bit mode
when "10" => rtx_engine.bytecnt <= "011"; spi_dat_o <= rtx_engine.sreg(23); -- 24-bit mode
when others => rtx_engine.bytecnt <= "100"; spi_dat_o <= rtx_engine.sreg(31); -- 32-bit mode
end case;
end process data_size;

Expand Down
28 changes: 14 additions & 14 deletions rtl/core/neorv32_top.vhd
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Expand Up @@ -166,8 +166,8 @@ entity neorv32_top is
-- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) --
xip_csn_o : out std_ulogic; -- chip-select, low-active
xip_clk_o : out std_ulogic; -- serial clock
xip_sdi_i : in std_ulogic := 'L'; -- device data input
xip_sdo_o : out std_ulogic; -- controller data output
xip_dat_i : in std_ulogic := 'L'; -- device data input
xip_dat_o : out std_ulogic; -- controller data output

-- GPIO (available if IO_GPIO_NUM > 0) --
gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
Expand All @@ -186,9 +186,9 @@ entity neorv32_top is
uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional

-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
spi_clk_o : out std_ulogic; -- SPI serial clock
spi_dat_o : out std_ulogic; -- controller data out, peripheral data in
spi_dat_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select

-- TWI (available if IO_TWI_EN = true) --
Expand Down Expand Up @@ -600,7 +600,7 @@ begin
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX
fast_irq(05) <= uart1_txd_irq; -- secondary UART (UART1) TX
fast_irq(06) <= spi_irq; -- SPI transfer done
fast_irq(06) <= spi_irq; -- SPI interrupt
fast_irq(07) <= twi_irq; -- TWI transfer done
fast_irq(08) <= xirq_irq; -- external interrupt controller
fast_irq(09) <= neoled_irq; -- NEOLED buffer IRQ
Expand Down Expand Up @@ -951,8 +951,8 @@ begin
-- SPI device interface --
spi_csn_o => xip_csn_o, -- chip-select, low-active
spi_clk_o => xip_clk_o, -- serial clock
spi_data_i => xip_sdi_i, -- device data output
spi_data_o => xip_sdo_o -- controller data output
spi_dat_i => xip_dat_i, -- device data output
spi_dat_o => xip_dat_o -- controller data output
);
resp_bus(RESP_XIP_CT).err <= '0'; -- no access error possible
end generate;
Expand All @@ -968,7 +968,7 @@ begin
xip_cg_en <= '0';
xip_csn_o <= '1';
xip_clk_o <= '0';
xip_sdo_o <= '0';
xip_dat_o <= '0';
end generate;


Expand Down Expand Up @@ -1246,9 +1246,9 @@ begin
clkgen_en_o => spi_cg_en, -- enable clock generator
clkgen_i => clk_gen,
-- com lines --
spi_sck_o => spi_sck_o, -- SPI serial clock
spi_sdo_o => spi_sdo_o, -- controller data out, peripheral data in
spi_sdi_i => spi_sdi_i, -- controller data in, peripheral data out
spi_clk_o => spi_clk_o, -- SPI serial clock
spi_dat_o => spi_dat_o, -- controller data out, peripheral data in
spi_dat_i => spi_dat_i, -- controller data in, peripheral data out
spi_csn_o => spi_csn_o, -- SPI CS
-- interrupt --
irq_o => spi_irq -- transmission done interrupt
Expand All @@ -1260,8 +1260,8 @@ begin
if (IO_SPI_EN = false) generate
resp_bus(RESP_SPI) <= resp_bus_entry_terminate_c;
--
spi_sck_o <= '0';
spi_sdo_o <= '0';
spi_clk_o <= '0';
spi_dat_o <= '0';
spi_csn_o <= (others => '1'); -- CS lines are low-active
spi_cg_en <= '0';
spi_irq <= '0';
Expand Down
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