[rtl] minor cleanup

CHANGELOG.md

@@ -32,6 +32,7 @@ mimpid = 0x01040312 => 01.04.03.12 => Version 01.04.03.12 => v1.4.3.12
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 14.08.2022 | 1.7.4.10 | cleanup of FIFO rtl component [#384](https://github.com/stnolting/neorv32/pull/384) |
 | 13.08.2022 | 1.7.4.9 | minor rtl cleanups and optimizations [#383](https://github.com/stnolting/neorv32/pull/383) |
 | 01.08.2022 | 1.7.4.8 | :sparkles: add configurable data FIFO to **SPI** module; [#381](https://github.com/stnolting/neorv32/pull/381) |
 | 31.07.2022 | 1.7.4.7 | :warning: rework **SLINK** module; [#377](https://github.com/stnolting/neorv32/pull/377) |

rtl/core/neorv32_cpu_control.vhd

@@ -494,7 +494,6 @@ begin
       clk_i   => clk_i,                -- clock, rising edge
       rstn_i  => '1',                  -- async reset, low-active
       clear_i => fetch_engine.restart, -- sync reset, high-active
-      level_o => open,
       half_o  => ipb.half(i),          -- at least half full
       -- write port --
       wdata_i => ipb.wdata(i),         -- write data
@@ -738,7 +737,6 @@ begin
     end if;
   end process execute_engine_fsm_sync;
 
-
   -- PC increment for next linear instruction (+2 for compressed instr., +4 otherwise) --
   execute_engine.next_pc_inc(data_width_c-1 downto 4) <= (others => '0');
   execute_engine.next_pc_inc(3 downto 0) <= x"4" when ((execute_engine.is_ci = '0') or (CPU_EXTENSION_RISCV_C = false)) else x"2";
@@ -933,14 +931,14 @@ begin
       -- ------------------------------------------------------------
         -- PC & IR update --
         execute_engine.pc_mux_sel <= '0'; -- next PC
+        execute_engine.pc_we      <= not execute_engine.branched; -- update PC with next_pc if there was no actual branch
         execute_engine.i_reg_nxt  <= issue_engine.data(31 downto 0);
         execute_engine.is_ci_nxt  <= issue_engine.data(32); -- this is a de-compressed instruction
         execute_engine.is_ici_nxt <= issue_engine.data(35); -- illegal compressed instruction
         --
         if (issue_engine.valid(0) = '1') or (issue_engine.valid(1) = '1') then -- instruction available?
-          -- PC update --
+          -- clear branch flipflop --
           execute_engine.branched_nxt <= '0';
-          execute_engine.pc_we        <= not execute_engine.branched; -- update PC with next_pc if there was no actual branch
           -- IR update - exceptions --
           trap_ctrl.instr_ma <= issue_engine.data(33) and (not bool_to_ulogic_f(CPU_EXTENSION_RISCV_C)); -- misaligned instruction fetch (if C disabled)
           trap_ctrl.instr_be <= issue_engine.data(34); -- bus access fault during instruction fetch

rtl/core/neorv32_fifo.vhd

@@ -1,5 +1,5 @@
 -- #################################################################################################
--- # << NEORV32 - General Purpose FIFO Component >>                                                #
+-- # << NEORV32 - Generic Single-Clock FIFO >>                                                     #
 -- # ********************************************************************************************* #
 -- # BSD 3-Clause License                                                                          #
 -- #                                                                                               #
@@ -51,7 +51,6 @@ entity neorv32_fifo is
     clk_i   : in  std_ulogic; -- clock, rising edge
     rstn_i  : in  std_ulogic; -- async reset, low-active
     clear_i : in  std_ulogic; -- sync reset, high-active
-    level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill level
     half_o  : out std_ulogic; -- FIFO is at least half full
     -- write port --
     wdata_i : in  std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data
@@ -73,7 +72,6 @@ architecture neorv32_fifo_rtl of neorv32_fifo is
     re    : std_ulogic; -- read enable
     w_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- write pointer
     r_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- read pointer
-    level : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill count
     data  : fifo_data_t; -- fifo memory
     buf   : std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- if single-entry FIFO
     match : std_ulogic;
@@ -100,9 +98,9 @@ begin
   fifo.we <= we_i when (FIFO_SAFE = false) else (we_i and fifo.free); -- SAFE = write only if space left
 
 
-  -- FIFO Control ---------------------------------------------------------------------------
+  -- FIFO Pointers --------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  fifo_control: process(rstn_i, clk_i)
+  fifo_pointers: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
       fifo.w_pnt <= (others => '0');
@@ -121,19 +119,18 @@ begin
         fifo.r_pnt <= std_ulogic_vector(unsigned(fifo.r_pnt) + 1);
       end if;
     end if;
-  end process fifo_control;
+  end process fifo_pointers;
 
-  -- status --
+
+  -- FIFO Status ----------------------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
   fifo.match <= '1' when (fifo.r_pnt(fifo.r_pnt'left-1 downto 0) = fifo.w_pnt(fifo.w_pnt'left-1 downto 0)) or (FIFO_DEPTH = 1) else '0';
   fifo.full  <= '1' when (fifo.r_pnt(fifo.r_pnt'left) /= fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0';
   fifo.empty <= '1' when (fifo.r_pnt(fifo.r_pnt'left)  = fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0';
   fifo.free  <= not fifo.full;
   fifo.avail <= not fifo.empty;
   level_diff <= std_ulogic_vector(unsigned(fifo.w_pnt) - unsigned(fifo.r_pnt));
-  fifo.level <= std_ulogic_vector(to_unsigned(FIFO_DEPTH, fifo.level'length)) when (fifo.full = '1') else level_diff;
 
-  -- status output --
-  level_o <= fifo.level;
   free_o  <= fifo.free;
   avail_o <= fifo.avail;
 
@@ -172,7 +169,7 @@ begin
   -- synchronous read --
   fifo_read_sync:
   if (FIFO_RSYNC = true) generate
-    fifo_memory_read: process(clk_i)
+    fifo_read: process(clk_i)
     begin
       if rising_edge(clk_i) then
         if (FIFO_DEPTH = 1) then
@@ -181,7 +178,7 @@ begin
           rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
         end if;
       end if;
-    end process fifo_memory_read;
+    end process fifo_read;
   end generate;
 
 

rtl/core/neorv32_neoled.vhd

@@ -294,7 +294,6 @@ begin
     clk_i   => clk_i,           -- clock, rising edge
     rstn_i  => '1',             -- async reset, low-active
     clear_i => tx_buffer.clear, -- sync reset, high-active
-    level_o => open,            -- fill level
     half_o  => tx_buffer.half,  -- FIFO is at least half full
     -- write port --
     wdata_i => tx_buffer.wdata, -- write data

rtl/core/neorv32_package.vhd

@@ -63,7 +63,7 @@ package neorv32_package is
   -- Architecture Constants (do not modify!) ------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   constant data_width_c : natural := 32; -- native data path width - do not change!
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070409"; -- NEORV32 version - no touchy!
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070410"; -- NEORV32 version - no touchy!
   constant archid_c     : natural := 19; -- official RISC-V architecture ID - hands off!
 
   -- Check if we're inside the Matrix -------------------------------------------------------
@@ -2138,7 +2138,6 @@ package neorv32_package is
       clk_i   : in  std_ulogic; -- clock, rising edge
       rstn_i  : in  std_ulogic; -- async reset, low-active
       clear_i : in  std_ulogic; -- sync reset, high-active
-      level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill level
       half_o  : out std_ulogic; -- FIFO is at least half full
       -- write port --
       wdata_i : in  std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data

rtl/core/neorv32_slink.vhd

@@ -290,7 +290,6 @@ begin
       clk_i                => clk_i,            -- clock, rising edge
       rstn_i               => '1',              -- async reset, low-active
       clear_i              => tx_fifo.clr(i),   -- sync reset, high-active
-      level_o              => open,             -- fill level
       half_o               => tx_fifo.half(i),  -- FIFO is at least half full
       wdata_i(31 downto 0) => tx_fifo.wdata(i), -- write data
       wdata_i(32)          => tx_fifo.wlast(i), -- end of packet
@@ -341,7 +340,6 @@ begin
       clk_i                => clk_i,            -- clock, rising edge
       rstn_i               => '1',              -- async reset, low-active
       clear_i              => rx_fifo.clr(i),   -- sync reset, high-active
-      level_o              => open,             -- fill level
       half_o               => rx_fifo.half(i),  -- FIFO is at least half full
       wdata_i(31 downto 0) => rx_fifo.wdata(i), -- write data
       wdata_i(32)          => rx_fifo.wlast(i), -- end of packet

rtl/core/neorv32_spi.vhd

@@ -249,7 +249,6 @@ begin
       clk_i   => clk_i,         -- clock, rising edge
       rstn_i  => '1',           -- async reset, low-active
       clear_i => tx_fifo.clear, -- sync reset, high-active
-      level_o => open,
       half_o  => tx_fifo.half,  -- FIFO at least half-full
       -- write port --
       wdata_i => tx_fifo.wdata, -- write data
@@ -286,7 +285,6 @@ begin
       clk_i   => clk_i,         -- clock, rising edge
       rstn_i  => '1',           -- async reset, low-active
       clear_i => rx_fifo.clear, -- sync reset, high-active
-      level_o => open,
       half_o  => rx_fifo.half,  -- FIFO at least half-full
       -- write port --
       wdata_i => rx_fifo.wdata, -- write data

rtl/core/neorv32_trng.vhd

@@ -205,7 +205,6 @@ begin
     clk_i   => clk_i,      -- clock, rising edge
     rstn_i  => '1',        -- async reset, low-active
     clear_i => fifo.clear, -- sync reset, high-active
-    level_o => open,
     half_o  => open,
     -- write port --
     wdata_i => fifo.wdata, -- write data

rtl/core/neorv32_uart.vhd

@@ -344,7 +344,6 @@ begin
     clk_i   => clk_i,           -- clock, rising edge
     rstn_i  => '1',             -- async reset, low-active
     clear_i => tx_buffer.clear, -- sync reset, high-active
-    level_o => open,
     half_o  => tx_buffer.half,  -- FIFO at least half-full
     -- write port --
     wdata_i => tx_buffer.wdata, -- write data
@@ -520,7 +519,6 @@ begin
     clk_i   => clk_i,           -- clock, rising edge
     rstn_i  => '1',             -- async reset, low-active
     clear_i => rx_buffer.clear, -- sync reset, high-active
-    level_o => open,
     half_o  => rx_buffer.half,  -- FIFO at least half-full
     -- write port --
     wdata_i => rx_buffer.wdata, -- write data