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add gate for CSR read address #295

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Apr 7, 2022
Merged

add gate for CSR read address #295

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2b7c620
add gate for CSR read address
stnolting Apr 7, 2022
ae21dcd
add v1.6.9.9
stnolting Apr 7, 2022
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3 changes: 2 additions & 1 deletion CHANGELOG.md
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Expand Up @@ -33,8 +33,9 @@ The version number is globally defined by the `hw_version_c` constant in the mai

| Date (*dd.mm.yyyy*) | Version | Comment |
|:----------:|:-------:|:--------|
| 07.04.2022 | 1.6.9.9 | AND-gate CSR read address: reduces **CPU switching activity** (= dynamic power consumption) and even reduces area costs; [PR #295](https://github.com/stnolting/neorv32/pull/295) |
| 06.04.2022 | 1.6.9.8 | :bug: fixed instruction decoding collision in CPU `B` extension; :lock: closed further illegal instruction encoding holes; optimized illegal instruction detection logic; [PR #294](https://github.com/stnolting/neorv32/pull/294) |
| 04.04.2022 | 1.6.9.7 | **major CPU logic optimization**: reduced area costs and shortened critical path (higher f_max!); :bug: fixed rare bug in RTE (if C-extension is not implemented); :lock: closed further illegal instruction encoding holes; [PR #293](https://github.com/stnolting/neorv32/pull/293) |
| 04.04.2022 | 1.6.9.7 | **major CPU logic optimization**: reduced area costs and shortened critical path (higher f_max!); :bug: fixed rare bug in RTE core (if C-extension is not implemented); :lock: closed further illegal instruction encoding holes; [PR #293](https://github.com/stnolting/neorv32/pull/293) |
| 01.04.2022 | 1.6.9.6 | rework **CPU front-end**: instruction issue engine; much cleaner code, slightly less HW required; [PR #292](https://github.com/stnolting/neorv32/pull/292) |
| 29.03.2022 | 1.6.9.5 | minor clock generator edits: reset **clock generator** explicitly if not being used by _any_ peripheral/IO device |
| 19.03.2022 | 1.6.9.4 | :test_tube: change usage of VHDL `*_reduce_f` functions for signals that might effect gate-level simulations; [PR #290](https://github.com/stnolting/neorv32/pull/290) |
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38 changes: 27 additions & 11 deletions rtl/core/neorv32_cpu_control.vhd
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Expand Up @@ -271,6 +271,8 @@ architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
addr : std_ulogic_vector(11 downto 0); -- csr address
we : std_ulogic; -- csr write enable
we_nxt : std_ulogic;
re : std_ulogic; -- csr read enable
re_nxt : std_ulogic;
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
--
Expand Down Expand Up @@ -916,6 +918,7 @@ begin

-- CSR access --
csr.we_nxt <= '0';
csr.re_nxt <= '0';

-- CONTROL DEFAULTS --
ctrl_nxt <= (others => '0'); -- default: all off
Expand Down Expand Up @@ -1017,18 +1020,18 @@ begin
-- co-processor MULDIV operation (multi-cycle) --
if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV
((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- trigger MULDIV CP
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_muldiv_c; -- trigger MULDIV CP
execute_engine.state_nxt <= ALU_WAIT;
-- co-processor BIT-MANIPULATION operation (multi-cycle) --
elsif (CPU_EXTENSION_RISCV_B = true) and
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_b_reg = '1')) or -- register operation
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_b_imm = '1'))) then -- immediate operation
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- trigger BITMANIP CP
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_bitmanip_c; -- trigger BITMANIP CP
execute_engine.state_nxt <= ALU_WAIT;
-- co-processor SHIFT operation (multi-cycle) --
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_shifter_c; -- trigger SHIFTER CP
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_shifter_c; -- trigger SHIFTER CP
execute_engine.state_nxt <= ALU_WAIT;
-- ALU CORE operation (single-cycle) --
else
Expand Down Expand Up @@ -1080,7 +1083,7 @@ begin
when opcode_fop_c => -- floating-point operations
-- ------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zfinx = true) then
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- trigger FPU CP
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_fpu_c; -- trigger FPU CP
execute_engine.state_nxt <= ALU_WAIT;
else
execute_engine.state_nxt <= DISPATCH;
Expand All @@ -1090,7 +1093,7 @@ begin
when opcode_cust0_c => -- CFU: custom RISC-V instructions (CUSTOM0 OPCODE space)
-- ------------------------------------------------------------
if (CPU_EXTENSION_RISCV_Zxcfu = true) then
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_cfu_c; -- trigger CFU CP
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_cfu_c; -- trigger CFU CP
execute_engine.state_nxt <= ALU_WAIT;
else
execute_engine.state_nxt <= DISPATCH;
Expand All @@ -1099,6 +1102,7 @@ begin

when opcode_system_c => -- environment/csr access
-- ------------------------------------------------------------
csr.re_nxt <= '1'; -- always read CSR, only relevant for CSR access
if (CPU_EXTENSION_RISCV_Zicsr = true) then
execute_engine.state_nxt <= SYSTEM;
else
Expand Down Expand Up @@ -1489,7 +1493,6 @@ begin
-- Trap Controller ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
trap_controller: process(rstn_i, clk_i)
variable mode_m_v, mode_u_v : std_ulogic;
begin
if (rstn_i = '0') then
trap_ctrl.exc_buf <= (others => '0');
Expand Down Expand Up @@ -1759,6 +1762,7 @@ begin
begin
if (rstn_i = '0') then
csr.we <= '0';
csr.re <= def_rst_val_c;
--
csr.mstatus_mie <= '0';
csr.mstatus_mpie <= '0';
Expand Down Expand Up @@ -1806,6 +1810,7 @@ begin
elsif rising_edge(clk_i) then
-- write access? --
csr.we <= csr.we_nxt and (not trap_ctrl.exc_buf(exc_iillegal_c)); -- write if not illegal instruction
csr.re <= csr.re_nxt;

-- defaults --
csr.mip_firq_nclr <= (others => '1'); -- active low
Expand Down Expand Up @@ -2098,17 +2103,28 @@ begin

-- Control and Status Registers - Read Access ---------------------------------------------
-- -------------------------------------------------------------------------------------------
csr_read_access: process(rstn_i, clk_i)
csr_read_access: process(clk_i)
variable csr_addr_v : std_ulogic_vector(11 downto 0);
begin
if rising_edge(clk_i) then
csr.rdata <= (others => '0'); -- default output, unimplemented CSRs are hardwired to zero
csr.rdata <= (others => '0'); -- default output, unimplemented CSRs read as zero
if (CPU_EXTENSION_RISCV_Zicsr = true) then
csr_addr_v(11 downto 10) := csr.addr(11 downto 10);
csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) CSRs ONLY !!!
csr_addr_v(07 downto 00) := csr.addr(07 downto 00);

-- AND-gate CSR read address: csr.rdata is zero if csr.re is not set --
if (csr.re = '1') then
csr_addr_v(11 downto 10) := csr.addr(11 downto 10);
csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) CSRS ONLY !!!
csr_addr_v(07 downto 00) := csr.addr(07 downto 00);
else -- reduce switching activity if not accessed
csr_addr_v := (others => '0'); -- = csr_zero_c
end if;
case csr_addr_v is

-- hardware-only CSRs --
-- --------------------------------------------------------------------
-- when csr_zero_c => -- zero (r/-): always returns zero, only relevant for hardware-access, not visible to ISA
-- csr.rdata <= (others => '0');

-- floating-point CSRs --
-- --------------------------------------------------------------------
when csr_fflags_c => -- fflags (r/w): floating-point (FPU) exception flags
Expand Down
5 changes: 2 additions & 3 deletions rtl/core/neorv32_package.vhd
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Expand Up @@ -65,7 +65,7 @@ package neorv32_package is
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060908"; -- NEORV32 version - no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060909"; -- NEORV32 version - no touchy!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!

-- Check if we're inside the Matrix -------------------------------------------------------
Expand Down Expand Up @@ -367,7 +367,6 @@ package neorv32_package is
constant ctrl_bus_de_lock_c : natural := 40; -- remove atomic/exclusive access
constant ctrl_bus_ch_lock_c : natural := 41; -- evaluate atomic/exclusive lock (SC operation)
-- alu co-processors --
constant ctrl_cp_id_lsb_c : natural := 42; -- cp select ID lsb [ALIAS]
constant ctrl_cp_trig0_c : natural := 42; -- trigger CP0
constant ctrl_cp_trig1_c : natural := 43; -- trigger CP1
constant ctrl_cp_trig2_c : natural := 44; -- trigger CP2
Expand All @@ -376,7 +375,6 @@ package neorv32_package is
constant ctrl_cp_trig5_c : natural := 47; -- trigger CP5
constant ctrl_cp_trig6_c : natural := 48; -- trigger CP6
constant ctrl_cp_trig7_c : natural := 49; -- trigger CP7
constant ctrl_cp_id_msb_c : natural := 49; -- cp select ID msb [ALIAS]
-- instruction word control blocks (used by cpu co-processors) --
constant ctrl_ir_funct3_0_c : natural := 50; -- funct3 bit 0
constant ctrl_ir_funct3_1_c : natural := 51; -- funct3 bit 1
Expand Down Expand Up @@ -554,6 +552,7 @@ package neorv32_package is

-- RISC-V CSR Addresses -------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant csr_zero_c : std_ulogic_vector(11 downto 0) := x"000"; -- always returns zero, only relevant for hardware access
-- <<< standard read/write CSRs >>> --
-- user floating-point CSRs --
constant csr_class_float_c : std_ulogic_vector(09 downto 0) := x"00" & "00"; -- floating point
Expand Down