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Fix some typos. #286

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Mar 10, 2022
Merged

Fix some typos. #286

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8 changes: 4 additions & 4 deletions rtl/README.md
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
## HArdware RTL Sources
## Hardware RTL Sources


### [`core`](https://github.com/stnolting/neorv32/tree/main/rtl/core)
Expand All @@ -12,21 +12,21 @@ contains the _platform-agnostic_ VHDL architectures of the processor-internal me
You can _replace_ inclusion of these files by platform-optimized memory architectures.


### [`processor_templates`](https://github.com/stnolting/neorv32/tree/main/rtl/processor_templates`)
### [`processor_templates`](https://github.com/stnolting/neorv32/tree/main/rtl/processor_templates)

Contains pre-configured "SoC" templates that instantiate the processor's top entity from `core`.
These templates can be instantiated directly within a FPGA-specific board wrapper.


### [`system_integration`](https://github.com/stnolting/neorv32/tree/main/rtl/system_integration`)
### [`system_integration`](https://github.com/stnolting/neorv32/tree/main/rtl/system_integration)

Top entities in this folder provide the same peripheral/IO signals and configuration generics as the default
processor top entity from `core`, but feature a different interface type.
For example: an **AXI4-Lite**-compatible bus interface instead of the default Wishbone bus interface
or a top entity with _resolved_ port signal types.


### [`test_setups`](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups`)
### [`test_setups`](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups)

Minimal test setups (FPGA- and board-independent) for the processor. See the
[README](https://github.com/stnolting/neorv32/tree/main/rtl/test_setups)
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