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[rtl] add err_o signal to IMEM modules #273

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merged 8 commits into from
Feb 5, 2022
Merged

[rtl] add err_o signal to IMEM modules #273

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01f5b32
[rtl/core] add err_o signal to IMEM modules
stnolting Feb 5, 2022
584c3e9
[sim] add err_o signal to sim-only IMEM modules
stnolting Feb 5, 2022
e0b6c18
[docs/datasheet] add note regarding write-accesses to read-only IMEM
stnolting Feb 5, 2022
2d02ad6
[CHANGELOG] add v1.6.7.4
stnolting Feb 5, 2022
9c82cfc
[CHANGELOG] minor edits
stnolting Feb 5, 2022
1297d4f
[docs/datasheet] IMEM: minor edit
stnolting Feb 5, 2022
09ac572
[rtl/core] added err_o signal to BOOTROM
stnolting Feb 5, 2022
7eb1ef6
[docs/datasheet] added note regarding write-accesses to the BOOTROM
stnolting Feb 5, 2022
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -32,6 +32,7 @@ The version number is globally defined by the `hw_version_c` constant in the mai

| Date (*dd.mm.yyyy*) | Version | Comment |
|:----------:|:-------:|:--------|
| 05.02.2022 | 1.6.7.4 | added `err_o` signal to **IMEM** module; if the IMEM is implemented as true ROM any write attempt will raise a _store access fault_ exception (with a `[DEVICE_ERR]` error); see [PR #273](https://github.com/stnolting/neorv32/pull/273) |
| 03.02.2022 | 1.6.7.3 | using `LTO` (link-time-optimization) option for **bootloader**; improved bootloader user console; see [PR #268](https://github.com/stnolting/neorv32/pull/268) |
| 31.01.2022 | 1.6.7.2 | :bug: fixed minor bug in **bootloader'd MTIME handling** (bootloader crashed if `Zicntr` ISA extension not enabled), fixed minor issues in MTIME and `time` CSRs handling; added MTIME example program; see [PR #267](https://github.com/stnolting/neorv32/pull/267) |
| 30.01.2022 | 1.6.7.1 | :sparkles: added **`Zxcfu` ISA extension for user-defined custom RISC-V instructions**; see [PR #264](https://github.com/stnolting/neorv32/pull/264) |
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3 changes: 3 additions & 0 deletions docs/datasheet/soc_bootrom.adoc
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Expand Up @@ -30,6 +30,9 @@ The bootloader memory is _read-only_ and is automatically initialized with the b
determined via synthesis and expanded to the next power of two. For example, if the bootloader code requires
10kB of storage, a ROM with 16kB will be generated. The maximum size must not exceed 32kB.

[NOTE]
Any write access to the BOOTROM will raise a _store access fault_ exception.

.Bootloader - Software
[TIP]
See section <<_bootloader>> for more information regarding the actual bootloader software/executable itself.
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5 changes: 4 additions & 1 deletion docs/datasheet/soc_imem.adoc
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Expand Up @@ -11,7 +11,7 @@
| Top entity port: | none |
| Configuration generics: | _MEM_INT_IMEM_EN_ | implement processor-internal IMEM when _true_
| | _MEM_INT_IMEM_SIZE_ | IMEM size in bytes
| | _INT_BOOTLOADER_EN_ | use internal bootloader when _true_ (implements IMEM as _uninitialized_ RAM)
| | _INT_BOOTLOADER_EN_ | use internal bootloader when _true_ (implements IMEM as _uninitialized_ RAM, otherwise the IMEM is implemented an _pre-intialized_ ROM)
| CPU interrupts: | none |
|=======================

Expand All @@ -37,3 +37,6 @@ architecture definition (`mem/neorv32_imem.default.vhd`). This **default archite
_platform independent_ memory design that (should) infers embedded memory block. You can replace/modify the architecture
source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping
and/or timing.

[NOTE]
If the IMEM is implemented as true ROM any write attempt to it will raise a _store access fault_ exception.
4 changes: 3 additions & 1 deletion rtl/core/mem/neorv32_imem.default.vhd
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Expand Up @@ -6,7 +6,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -166,8 +166,10 @@ begin
rden <= acc_en and rden_i;
if (IMEM_AS_IROM = true) then
ack_o <= acc_en and rden_i;
err_o <= acc_en and wren_i;
else
ack_o <= acc_en and (rden_i or wren_i);
err_o <= '0';
end if;
end if;
end process bus_feedback;
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4 changes: 3 additions & 1 deletion rtl/core/mem/neorv32_imem.legacy.vhd
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Expand Up @@ -6,7 +6,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -163,8 +163,10 @@ begin
rden <= acc_en and rden_i;
if (IMEM_AS_IROM = true) then
ack_o <= acc_en and rden_i;
err_o <= acc_en and wren_i;
else
ack_o <= acc_en and (rden_i or wren_i);
err_o <= '0';
end if;
end if;
end process bus_feedback;
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9 changes: 6 additions & 3 deletions rtl/core/neorv32_boot_rom.vhd
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Expand Up @@ -3,7 +3,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -47,9 +47,11 @@ entity neorv32_boot_rom is
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic -- transfer error
);
end neorv32_boot_rom;

Expand Down Expand Up @@ -91,7 +93,8 @@ begin
mem_file_access: process(clk_i)
begin
if rising_edge(clk_i) then
rden <= rden_i and acc_en;
rden <= acc_en and rden_i;
err_o <= acc_en and wren_i;
if (acc_en = '1') then -- reduce switching activity when not accessed
rdata <= mem_rom(to_integer(unsigned(addr)));
end if;
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5 changes: 3 additions & 2 deletions rtl/core/neorv32_imem.entity.vhd
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Expand Up @@ -6,7 +6,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -53,6 +53,7 @@ entity neorv32_imem is
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic -- transfer error
);
end neorv32_imem;
9 changes: 6 additions & 3 deletions rtl/core/neorv32_package.vhd
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Expand Up @@ -63,7 +63,7 @@ package neorv32_package is
-- Architecture Constants (do not modify!) ------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- native data path width - do not change!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060703"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060704"; -- no touchy!
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!

-- Check if we're inside the Matrix -------------------------------------------------------
Expand Down Expand Up @@ -1599,7 +1599,8 @@ package neorv32_package is
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic -- transfer error
);
end component;

Expand Down Expand Up @@ -1631,9 +1632,11 @@ package neorv32_package is
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(31 downto 0); -- address
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
ack_o : out std_ulogic; -- transfer acknowledge
err_o : out std_ulogic -- transfer error
);
end component;

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9 changes: 5 additions & 4 deletions rtl/core/neorv32_top.vhd
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Expand Up @@ -748,9 +748,9 @@ begin
addr_i => p_bus.addr, -- address
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_IMEM).rdata, -- data out
ack_o => resp_bus(RESP_IMEM).ack -- transfer acknowledge
ack_o => resp_bus(RESP_IMEM).ack, -- transfer acknowledge
err_o => resp_bus(RESP_IMEM).err -- transfer error
);
resp_bus(RESP_IMEM).err <= '0'; -- no access error possible
end generate;

neorv32_int_imem_inst_false:
Expand Down Expand Up @@ -798,11 +798,12 @@ begin
port map (
clk_i => clk_i, -- global clock line
rden_i => p_bus.re, -- read enable
wren_i => p_bus.we, -- write enable
addr_i => p_bus.addr, -- address
data_o => resp_bus(RESP_BOOTROM).rdata, -- data out
ack_o => resp_bus(RESP_BOOTROM).ack -- transfer acknowledge
ack_o => resp_bus(RESP_BOOTROM).ack, -- transfer acknowledge
err_o => resp_bus(RESP_BOOTROM).err -- transfer error
);
resp_bus(RESP_BOOTROM).err <= '0'; -- no access error possible
end generate;

neorv32_boot_rom_inst_false:
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3 changes: 2 additions & 1 deletion sim/simple/neorv32_imem.iram.simple.vhd
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Expand Up @@ -6,7 +6,7 @@
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
Expand Down Expand Up @@ -125,6 +125,7 @@ begin
begin
if rising_edge(clk_i) then
rden <= acc_en and rden_i;
err_o <= '0';
ack_o <= acc_en and (rden_i or wren_i);
end if;
end process bus_feedback;
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3 changes: 2 additions & 1 deletion sim/simple/neorv32_imem.simple.vhd
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Expand Up @@ -78,7 +78,8 @@ begin
begin
if rising_edge(clk_i) then
rden <= acc_en and rden_i;
ack_o <= acc_en and (rden_i or wren_i);
ack_o <= acc_en and rden_i;
err_o <= acc_en and wren_i;
addr_v := to_integer(unsigned(addr));
--
rdata <= (others => '0');
Expand Down