Adding the possibility of indicate external sources throw a enviromen…

setups/README.md

@@ -36,6 +36,7 @@ Project maintainers may make pull requests against this repository to [add or li
 | :file_folder: [`AlhambraII`](https://github.com/stnolting/neorv32/tree/master/setups/osflow)  | GHDL, Yosys, nextPNR | [AlhambraII](https://alhambrabits.com/alhambra/)                                                             | Lattice iCE40HX4K                         | [zipotron](https://github.com/zipotron) |
 | :file_folder: [`Orange Crab`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [Orange Crab](https://github.com/gregdavill/OrangeCrab)                                                      | Lattice ECP5-25F                          | [umarcor](https://github.com/umarcor), [jeremyherbert](https://github.com/jeremyherbert) |
 | :file_folder: [`ULX3S`](https://github.com/stnolting/neorv32/tree/master/setups/osflow)       | GHDL, Yosys, nextPNR | [ULX3S](https://radiona.org/ulx3s/)                                                                          | Lattice ECP5 `LFE5U-85F-6BG381C`          | [zipotron](https://github.com/zipotron) |
+| :earth_africa: [`ULX3S-SDRAM`](https://github.com/zipotron/neorv32-complex-setups)            | GHDL, Yosys, nextPNR | [ULX3S](https://radiona.org/ulx3s/)                                                                          | Lattice ECP5 `LFE5U-85F-6BG381C`          | [zipotron](https://github.com/zipotron) |
 
 :information_source: All setups using open-source toolchains are located in the
 [`osflow`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) folder.

setups/osflow/filesets.mk

@@ -48,7 +48,8 @@ NEORV32_CORE_SRC := \
 # Before including this partial makefile, NEORV32_MEM_SRC needs to be set
 # (containing two VHDL sources: one for IMEM and one for DMEM)
 
-NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} ${NEORV32_MEM_SRC} ${NEORV32_CORE_SRC}
+NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} ${NEORV32_MEM_SRC} ${NEORV32_MEM_SRC_EXTRA} ${NEORV32_CORE_SRC} ${NEORV32_CORE_SRC_EXTRA}
+NEORV32_VERILOG_ALL := ${NEORV32_VERILOG_SRC} ${NEORV32_VERILOG_SRC_EXTRA}
 
 ICE40_SRC := \
   devices/ice40/sb_ice40_components.vhd

setups/osflow/synthesis.mk

@@ -7,10 +7,10 @@ neorv32-obj08.cf: ${DEVICE_LIB}-obj08.cf ${NEORV32_SRC}
 work-obj08.cf: neorv32-obj08.cf ${DESIGN_SRC} ${BOARD_SRC}
 	ghdl -a $(GHDL_FLAGS) --work=work ${DESIGN_SRC} ${BOARD_SRC}
 
-${IMPL}.json: work-obj08.cf $(NEORV32_VERILOG_SRC)
+${IMPL}.json: work-obj08.cf $(NEORV32_VERILOG_ALL)
 	$(YOSYS) $(YOSYSFLAGS) \
 	  -p \
 	  "$(GHDLSYNTH) $(GHDL_FLAGS) --no-formal $(TOP); \
 	  synth_${YOSYSSYNTH} \
 	  -top $(TOP) $(YOSYSPIPE) \
-	  -json $@" $(NEORV32_VERILOG_SRC) 2>&1 | tee yosys-report.txt
+	  -json $@" $(NEORV32_VERILOG_ALL) 2>&1 | tee yosys-report.txt