simulation cycle signal of instruction memory

[rafaelcorsi]

The external Instruction memory (a) should check for the it valid cycle signal not for the b external memory signal:

neorv32/sim/neorv32_tb.vhd

Line 544 in 3be750c

if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_a.ack = '0') then

+(wb_mem_a.cyc = '1')
-(wb_mem_b.cyc = '1')

If its is correct I could generate a PR.

all the best,

[stnolting]

You are right, this seems to be a typo 🙈

If its is correct I could generate a PR.

👍