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OrangeCrab, bootloader and QSPI #103
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Btw, qSPI support sounds interesting. Maybe this is something we could add to the default NEORV32 SPI module. |
Yes, my mistake on the flash (sorry, it was late at night and my brain had already gone to sleep). QSPI in the core itself would make a lot of sense, especially if this could eventually be used for execute-in-place. |
QSPI should be no problem I think. SPI is just a shift register, classic SPI uses 1 bit and shifts by 1 position and QSPI uses 4 bits and shifts by 4 positions. So I think this could be also supported via a new configuration flag in the module. Directly executing code "in-place" via SPI is not supported as the SPI controller is a peripheral. Hence, any CPU-SPI access is not "transparent" for CPU (CPU accesses are not directly transformed into SPI transmissions). This could be emulated in software via some virtualization approach. Anyway, an external component that directly transforms bus accesses into SPI transactions seem to be a nice idea. Especially in combination with the instruction cache. |
I have implemented a Wishbone-to-SPI bridge supporting XIP: -> #224 |
Coming from #98.
/cc @jeremyherbert
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