Fix-up the litex wrapper (#722)

stnolting · Nov 9, 2023 · c5cff6d · c5cff6d
2 parents 6e0197e + 8211c76
commit c5cff6d
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/rtl/system_integration/neorv32_litex_core_complex.vhd b/rtl/system_integration/neorv32_litex_core_complex.vhd
@@ -95,7 +95,7 @@ entity neorv32_litex_core_complex is
     wb_dat_i    : in  std_ulogic_vector(31 downto 0); -- read data
     wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
     wb_we_o     : out std_ulogic; -- read/write
-    wb_sel_o    : out std_ulogic_vector(03 downto 0); -- byte enable
+    wb_sel_o    : out std_ulogic_vector(3 downto 0); -- byte enable
     wb_stb_o    : out std_ulogic; -- strobe
     wb_cyc_o    : out std_ulogic; -- valid cycle
     wb_ack_i    : in  std_ulogic; -- transfer acknowledge
@@ -199,7 +199,7 @@ begin
     -- External memory interface (WISHBONE) --
     MEM_EXT_EN                 => true,                           -- implement external memory bus interface?
     MEM_EXT_TIMEOUT            => wb_timeout_c,                   -- cycles after a pending bus access auto-terminates (0 = disabled)
-    MEM_EXT_PIPE_MODE          => true,                           -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
+    MEM_EXT_PIPE_MODE          => false,                           -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
     MEM_EXT_BIG_ENDIAN         => big_endian_c,                   -- byte order: true=big-endian, false=little-endian
     MEM_EXT_ASYNC_RX           => true,                           -- use register buffer for RX data when false
     MEM_EXT_ASYNC_TX           => true,                           -- use register buffer for TX data when false