[docs/src_adoc] CPU/processor/project is LITTLE-ENDIAN #50

stnolting · Jun 1, 2021 · 9604710 · 9604710
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diff --git a/docs/src_adoc/cpu.adoc b/docs/src_adoc/cpu.adoc
@@ -15,7 +15,7 @@ image::riscv_logo.png[width=350,align=center]
 * Optional hardware performance monitors (HPM) for application benchmarking
 * Separated interfaces for instruction fetch and data access (merged into single bus via a bus switch for
 the NEORV32 processor)
-* BIG-endian byte order
+* little-endian byte order
 * Configurable hardware reset
 * No hardware support of unaligned data/instruction accesses – they will trigger an exception. If the C extension is enabled instructions
 can also be 16-bit aligned and a misaligned instruction address exception is not possible anymore
@@ -201,10 +201,6 @@ OK: 1/1 RISCV_TARGET=neorv32 RISCV_DEVICE=Zifencei XLEN=32
 This list shows the currently known issues regarding full RISC-V-compatibility. More specific information
 can be found in section <<_instruction_sets_and_extensions>>.
 
-[IMPORTANT]
-CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus
-interface provides big- and little-endian configurations. See section <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
-
 [IMPORTANT]
 The `misa` CSR is read-only. It shows the synthesized CPU extensions. Hence, all implemented
 CPU extensions are always active and cannot be enabled/disabled dynamically during runtime. Any

diff --git a/docs/src_adoc/index.adoc b/docs/src_adoc/index.adoc
@@ -2,7 +2,7 @@
 :author: Dipl.-Ing. Stephan Nolting
 :email: stnolting@gmail.com
 :description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
-:revnumber: v1.5.5.9
+:revnumber: v1.5.5.13
 :doctype: book
 :sectnums:
 :icons: font

diff --git a/docs/src_adoc/neorv32.adoc b/docs/src_adoc/neorv32.adoc
@@ -2,7 +2,7 @@
 :author: Dipl.-Ing. Stephan Nolting
 :email: stnolting@gmail.com
 :description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
-:revnumber: v1.5.5.9
+:revnumber: v1.5.5.13
 :doctype: book
 :sectnums:
 :icons: image