[docs] update cache sections

stnolting · Mar 16, 2024 · 814d5a2 · 814d5a2
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diff --git a/docs/datasheet/soc_dcache.adoc b/docs/datasheet/soc_dcache.adoc
@@ -5,40 +5,33 @@
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 |=======================
-| Hardware source file(s): | neorv32_dcache.vhd  | 
+| Hardware source file(s): | neorv32_cache.vhd   | Generic cache module
 | Software driver file(s): | none                | _implicitly used_
-| Top entity port:         | none                | 
+| Top entity port:         | none                |
 | Configuration generics:  | `DCACHE_EN`         | implement processor-internal data cache when `true`
 |                          | `DCACHE_NUM_BLOCKS` | number of cache blocks (pages/lines)
 |                          | `DCACHE_BLOCK_SIZE` | size of a cache block in bytes
-| CPU interrupts:          | none | 
+| CPU interrupts:          | none |
 |=======================
 
 The processor features an optional data cache to improve performance when using memories with high
-access latencies. The cache is directly connected to the CPU's data access interface and provides
-full-transparent buffering.
-
-The cache is implemented if the `DCACHE_EN` generic is `true`. The size of the cache memory is defined via the
-`DCACHE_BLOCK_SIZE` (the size of a single cache block/page/line in bytes; has to be a power of two and greater than or
-equal to 4 bytes) and `DCACHE_NUM_BLOCKS` (the total amount of cache blocks; has to be a power of two and greater than or
-equal to 1) generics. The data cache provides only a single set, hence it is direct-mapped.
-
-
-**Cached/Uncached Accesses**
+access latencies. The cache is connected directly to the CPU's data access interface and provides
+full-transparent accesses. The cache is direct-mapped and uses "write-allocate" and "write-back" strategies.
 
+.Cached/Uncached Accesses
+[NOTE]
 The data cache provides direct accesses (= uncached) to memory in order to access memory-mapped IO (like the
 processor-internal IO/peripheral modules). All accesses that target the address range from `0xF0000000` to `0xFFFFFFFF`
 will not be cached at all (see section <<_address_space>>).
 
 .Caching Internal Memories
 [NOTE]
-The data cache is intended to accelerate data access to **processor-external** memories
-(via the external bus interface or via the XIP module). The cache(s) should not be implemented
-when using only processor-internal data and instruction memories.
+The data cache is intended to accelerate data access to **processor-external** memories.
+The CPU cache(s) should not be implemented when using only processor-internal data and instruction memories.
 
-.Manual Cache Clear/Reload
+.Manual Cache Flush/Clear/Reload
 [NOTE]
-By executing the `fence(.i)` instruction the cache is cleared and a reload from main memory is triggered.
+By executing the `fence(.i)` instruction the cache is flushed, cleared and a reload from main memory is triggered.
 
 .Retrieve Cache Configuration from Software
 [TIP]

diff --git a/docs/datasheet/soc_icache.adoc b/docs/datasheet/soc_icache.adoc
@@ -5,39 +5,29 @@
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 |=======================
-| Hardware source file(s): | neorv32_icache.vhd     | 
-| Software driver file(s): | none                   | _implicitly used_
-| Top entity port:         | none                   | 
-| Configuration generics:  | `ICACHE_EN`            | implement processor-internal instruction cache when `true`
-|                          | `ICACHE_NUM_BLOCKS`    | number of cache blocks (pages/lines)
-|                          | `ICACHE_BLOCK_SIZE`    | size of a cache block in bytes
-|                          | `ICACHE_ASSOCIATIVITY` | associativity / number of sets
-| CPU interrupts:          | none | 
+| Hardware source file(s): | neorv32_cache.vhd   | Generic cache module
+| Software driver file(s): | none                | _implicitly used_
+| Top entity port:         | none                |
+| Configuration generics:  | `ICACHE_EN`         | implement processor-internal instruction cache when `true`
+|                          | `ICACHE_NUM_BLOCKS` | number of cache blocks (pages/lines)
+|                          | `ICACHE_BLOCK_SIZE` | size of a cache block in bytes
+| CPU interrupts:          | none |
 |=======================
 
 The processor features an optional instruction cache to improve performance when using memories with high
-access latencies. The cache is directly connected to the CPU's instruction fetch interface and provides
-full-transparent buffering of instruction fetch accesses to the **entire address space**.
-
-The cache is implemented if the `ICACHE_EN` generic is `true`. The size of the cache memory is defined via
-`ICACHE_BLOCK_SIZE` (the size of a single cache block/page/line in bytes; has to be a power of two and greater than or
-equal to 4 bytes), `ICACHE_NUM_BLOCKS` (the total amount of cache blocks; has to be a power of two and greater than or
-equal to 1) and the actual cache associativity `ICACHE_ASSOCIATIVITY` (number of sets; 1 = direct-mapped, 2 = 2-way
-set-associative) generics. If the cache associativity is greater than one the LRU replacement policy (least recently
-used) is used.
-
-
-**Cached/Uncached Accesses**
+access latencies. The cache is connected directly to the CPU's instruction fetch interface and provides
+full-transparent accesses. The cache is direct-mapped and read-only.
 
+.Cached/Uncached Accesses
+[NOTE]
 The data cache provides direct accesses (= uncached) to memory in order to access memory-mapped IO (like the
 processor-internal IO/peripheral modules). All accesses that target the address range from `0xF0000000` to `0xFFFFFFFF`
 will not be cached at all (see section <<_address_space>>).
 
 .Caching Internal Memories
 [NOTE]
-The instruction cache is intended to accelerate instruction fetches from **processor-external** memories
-(via the external bus interface or via the XIP module). The cache(s) should not be implemented
-when using only processor-internal data and instruction memories.
+The data cache is intended to accelerate data access to **processor-external** memories.
+The CPU cache(s) should not be implemented when using only processor-internal data and instruction memories.
 
 .Manual Cache Clear/Reload
 [NOTE]

diff --git a/docs/datasheet/soc_xbus.adoc b/docs/datasheet/soc_xbus.adoc
@@ -6,7 +6,7 @@
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 |=======================
 | Hardware source file(s): | neorv32_xbus.vhd        | External bus gateway
-|                          | neorv32_cache.vhd       | External bus cache instance
+|                          | neorv32_cache.vhd       | Generic cache module
 | Software driver file(s): | none                    | _implicitly used_
 | Top entity port(s):      | `xbus_adr_o`            | address output (32-bit)
 |                          | `xbus_dat_i`            | data input (32-bit)

diff --git a/docs/datasheet/soc_xip.adoc b/docs/datasheet/soc_xip.adoc
@@ -5,18 +5,19 @@
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 |=======================
-| Hardware source file(s): | neorv32_xip.vhd |
-| Software driver file(s): | neorv32_xip.c |
-|                          | neorv32_xip.h |
-| Top entity port:         | `xip_csn_o` | 1-bit chip select, low-active
-|                          | `xip_clk_o` | 1-bit serial clock output
-|                          | `xip_dat_i` | 1-bit serial data input
-|                          | `xip_dat_o` | 1-bit serial data output
+| Hardware source file(s): | neorv32_xip.vhd        | XIP module
+|                          | neorv32_cache.vhd      | Generic cache module
+| Software driver file(s): | neorv32_xip.c          |
+|                          | neorv32_xip.h          |
+| Top entity port:         | `xip_csn_o`            | 1-bit chip select, low-active
+|                          | `xip_clk_o`            | 1-bit serial clock output
+|                          | `xip_dat_i`            | 1-bit serial data input
+|                          | `xip_dat_o`            | 1-bit serial data output
 | Configuration generics:  | `XIP_EN`               | implement XIP module when `true`
 |                          | `XIP_CACHE_EN`         | implement XIP cache when `true`
 |                          | `XIP_CACHE_NUM_BLOCKS` | number of blocks in XIP cache; has to be a power of two
 |                          | `XIP_CACHE_BLOCK_SIZE` | number of bytes per XIP cache block; has to be a power of two, min 4
-| CPU interrupts:          | none |
+| CPU interrupts:          | none                   |
 |=======================
 
 
@@ -190,7 +191,7 @@ The XIP cache is cleared when the XIP module is disabled (`XIP_CTRL_EN = 0`), wh
 [options="header",grid="all"]
 |=======================
 | Address | Name [C] | Bit(s), Name [C] | R/W | Function
-.15+<| `0xffffff40` .15+<| `CTRL` <|`0`     `XIP_CTRL_EN`                                       ^| r/w <| XIP module enable
+.14+<| `0xffffff40` .14+<| `CTRL` <|`0`     `XIP_CTRL_EN`                                       ^| r/w <| XIP module enable
                                   <|`3:1`   `XIP_CTRL_PRSC2 : XIP_CTRL_PRSC0`                   ^| r/w <| 3-bit SPI clock prescaler select
                                   <|`4`     `XIP_CTRL_CPOL`                                     ^| r/w <| SPI clock polarity
                                   <|`5`     `XIP_CTRL_CPHA`                                     ^| r/w <| SPI clock phase
@@ -200,9 +201,8 @@ The XIP cache is cleared when the XIP module is disabled (`XIP_CTRL_EN = 0`), wh
                                   <|`20:13` `XIP_CTRL_RD_CMD_MSB : XIP_CTRL_RD_CMD_LSB`         ^| r/w <| Flash read command
                                   <|`21`    `XIP_CTRL_SPI_CSEN`                                 ^| r/w <| Allow SPI chip-select to be actually asserted when set
                                   <|`22`    `XIP_CTRL_HIGHSPEED`                                ^| r/w <| enable SPI high-speed mode (ignoring `XIP_CTRL_PRSCx`)
-                                  <|`23:26` `XIP_CTRL_CDIV3 : XIP_CTRL_CDIV0`                   ^| r/- <| 4-bit clock divider for fine-tuning
-                                  <|`27:28` -                                                   ^| r/- <| _reserved_, read as zero
-                                  <|`29`    `XIP_CTRL_BURST_EN`                                 ^| r/- <| XIP burst mode enabled (if XIP cache is implemented)
+                                  <|`26:23` `XIP_CTRL_CDIV3 : XIP_CTRL_CDIV0`                   ^| r/- <| 4-bit clock divider for fine-tuning
+                                  <|`29:27` -                                                   ^| r/- <| _reserved_, read as zero
                                   <|`30`    `XIP_CTRL_PHY_BUSY`                                 ^| r/- <| SPI PHY busy when set
                                   <|`31`    `XIP_CTRL_XIP_BUSY`                                 ^| r/- <| XIP access in progress when set
 | `0xffffff44` | _reserved_ |`31:0` | r/- | _reserved_, read as zero