[docs] minor edits

docs/datasheet/soc.adoc

@@ -190,7 +190,7 @@ using the provided simulation/GHDL scripts to verify the configuration of the pr
 
 .Table Abbreviations
 [NOTE]
-The generic type "suv(x:y)" defines a `std_ulogic_vector(x downto y)`.
+The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downto y)`".
 
 
 .NEORV32 Processor Generic List
@@ -561,25 +561,25 @@ and the instruction returns a "failed" state.
 
 The reservation is invalidated if...
 
-* ... another `lr.w` instruction is executed
-* ... a normal store access to the reservated address takes place (by the CPU or by the DMA)
-* ... a hardware reset is triggered
-* Traps, interrupts, changes of privilege level, etc. do not alter the state of the reservation set at all.
+* ... another `lr.w` instruction is executed.
+* ... a normal store access to the reservated address takes place (by the CPU or by the DMA).
+* ... a hardware reset is triggered.
 
 .Strong Semantic
-[NOTE]
-The LR/SC mechanism follows the _strong_ semantic approach: the LL/SC instruction pair fails only if there is an
+[IMPORTANT]
+The LR/SC mechanism follows the _strong semantic_ approach: the LL/SC instruction pair fails only if there is a write
 access to the referenced memory location between the LL and SC instructions (by the CPU itself or by the DMA).
-Context changes, interrupts, traps, etc. do not effect the reservation state at all.
+Context changes, interrupts, traps, etc. do not effect nor invalidate the reservation state at all.
 
 The controller supports only a single global reservation set. By default this reservation set "monitors" a word-aligned
 4-byte granule. However, the granularity can be customized via the `AMO_RVS_GRANULARITY` top entity generic (see
-<<_processor_top_entity_generics>>).
+<<_processor_top_entity_generics>>) to cover an arbitrarily large naturally aligned address region. The only constraint is
+that the size of the address region has to be a power of two.
 
 .Physical Memory Attributes
 [NOTE]
 The reservation set can be set for _any_ address (only constrained by the configured granularity). This also
-includes cached memory, IO devices and processor-external modules.
+includes cached memory, memory-mapped IO devices and processor-external address spaces.
 
 Bus transactions triggered by the `lr.w` instruction register a new reservation set and are delegated to the adressed
 memory/device. Bus transactions triggered by the `sc.w` remove a reservation set and are forwarded to the adressed