Merge pull request #407 from stnolting/cpu_counters_cleanup

⚠️ [rtl] cleanup CPU standard counters, remove CPU_CNT_WIDTH generic

CHANGELOG.md

@@ -32,6 +32,7 @@ mimpid = 0x01040312 => 01.04.03.12 => Version 01.04.03.12 => v1.4.3.12
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 08.09.2022 | 1.7.6.4 | :warning: cleanup CPU standard counters and remove _CPU_CNT_WIDTH_ generic; [#407](https://github.com/stnolting/neorv32/pull/407) |
 | 07.09.2022 | 1.7.6.3 | minor rtl edits and cleanups; [#406](https://github.com/stnolting/neorv32/pull/406) |
 | 03.09.2022 | 1.7.6.2 | cleanup hardware reset logic; [#405](https://github.com/stnolting/neorv32/pull/405) |
 | 02.09.2022 | 1.7.6.1 | :sparkles: add new processor module: **1-Wire Interface Controller** (ONEWIRE); [#402](https://github.com/stnolting/neorv32/pull/402) |

docs/datasheet/cpu.adoc

@@ -598,18 +598,18 @@ will raise an illegal instruction exception if <<_mstatus>>`.TW` is set.
 ==== **`Zicntr`** CPU Base Counters
 
 The `Zicntr` ISA extension adds the basic cycle `[m]cycle[h]`), instruction-retired (`[m]instret[h]`) and time (`time[h]`)
-counters. This extensions is stated as _mandatory_ by the RISC-V spec. However, size-constrained setups may remove support for
+counters. This extensions is stated as _mandatory_ by the RISC-V spec. However, area-constrained setups may remove support for
 these counters. Section <<_machine_counter_and_timer_csrs>> shows a list of all `Zicntr`-related CSRs.
 These are available if the `Zicntr` ISA extensions is enabled via the <<_cpu_extension_riscv_zicntr>> generic.
 
 Additional CSRs:
 
 * <<_cycleh>>, <<_mcycleh>> - cycle counter
 * <<_instreth>>, <<_minstreth>> - instructions-retired counter
-* <<_timeh>> - system _wall-clock_ time
+* <<_timeh>> - system _wall-clock_ time (driven by the <<_machine_system_timer_mtime>>)
 
 [NOTE]
-Disabling the `Zicntr` extension does not remove the `time[h]`-driving MTIME unit.
+Disabling the `Zicntr` extension does not remove the `time[h]`-driving <<_machine_system_timer_mtime>>.
 
 If the `Zicntr` ISA extension is disabled, all accesses to the according counter CSRs will raise an illegal instruction exception.
 

docs/datasheet/cpu_csr.adoc

@@ -526,31 +526,15 @@ The two MSBs of each `pmpaddr` are hardwired to zero (= bits 33:32 of the physic
 :sectnums:
 ==== (Machine) Counter and Timer CSRs
 
-[NOTE]
-The <<_cpu_cnt_width>> generic defines the total size of the CPU's <<_cycleh>> and <<_instreth>>
-/ <<_mcycleh>> and <<_minstreth>>
-counter CSRs (low and high words combined); the time CSRs are not affected by this generic. Note that any
-configuration with <<_cpu_cnt_width>> less than 64 is not RISC-V compliant.
-
-.Effective CPU counter width (`[m]cycle` & `[m]instret`)
-[IMPORTANT]
-If _CPU_CNT_WIDTH_ is less than 64 (the default value) and greater than or equal 32, the according
-MSBs of `[m]cycleh` and `[m]instreth` are read-only and always read as zero. This configuration
-will also set the _CSR_MXISA_ZXSCNT_ flag ("small counters") in the <<_mxisa>> CSR. +
- +
-If _CPU_CNT_WIDTH_ is less than 32 and greater than 0, the `[m]cycleh` and `[m]instreth` CSRs are hardwired to zero
-and any write access to them is ignored. Furthermore, the according MSBs of `[m]cycle` and `[m]instret` are read-only
-and always read as zero. This configuration will also set the _CSR_MXISA_ZXSCNT_ flag ("small counters") in
-the <<_mxisa>> CSR. +
- +
-If _CPU_CNT_WIDTH_ is 0, the <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> CSRs are hardwired to zero
-and any write access to them is ignored.
-
 .Counter Reset
 [IMPORTANT]
 The counter CSRs do **not** provide a hardware reset. Hence, the CSRs have to be explicitly initialized by software
 before being used.
 
+.Counter Size
+[NOTE]
+When implemented (by enabling the `Zicntr` ISA extension) the standard CPU counters are always 64-bit wide (low-word + high-word).
+
 
 :sectnums!:
 ===== **`cycle[h]`**
@@ -826,7 +810,7 @@ NEORV32-specific read-only CSR that helps machine-mode software to discover `Z*`
 |  9    | _CSR_MXISA_ZIHPM_     | r/- | `Zihpm` (hardware performance monitors) extension available when set (via top's <<_cpu_extension_riscv_zihpm>> generic)
 |  8    | _CSR_MXISA_PMP_       | r/- | PMP` (physical memory protection) extension available when set (via top's <<_pmp_num_regions>> generic)
 |  7    | _CSR_MXISA_ZICNTR_    | r/- | `Zicntr` extension (`I` sub-extension) available when set - `[m]cycle`, `[m]instret` and `[m]time` CSRs available when set (via top's <<_cpu_extension_riscv_zicntr>> generic)
-|  6    | _CSR_MXISA_ZXSCNT_    | r/- | Custom extension - _Small_ CPU counters: `[m]cycle` & `[m]instret` CSRs have less than 64-bit when set (via top's <<_cpu_cnt_width>> generic)
+|  6    | -                     | r/- | _reserved_, read as zero
 |  5    | _CSR_MXISA_ZFINX_     | r/- | `Zfinx` extension (`F` sub-/alternative-extension: FPU using `x` registers) available when set (via top's <<_cpu_extension_riscv_zfinx>> generic)
 |  4    | -                     | r/- | _reserved_, read as zero
 |  3    | _CSR_MXISA_ZXCFU_     | r/- | `Zxcfu` extension (custom functions unit for custom RISC-V instructions) available when set (via top's <<_cpu_extension_riscv_zxcfu>> generic)

docs/datasheet/soc.adoc

@@ -448,20 +448,6 @@ The state of this generic can be retrieved by software via the <<_mxisa>> CSR.
 |======
 
 
-:sectnums!:
-===== _CPU_CNT_WIDTH_
-
-[cols="4,4,2"]
-[frame="all",grid="none"]
-|======
-| **CPU_CNT_WIDTH** | _natural_ | 64
-3+| This generic configures the total size of the CPU's <<_mcycleh>> and <<_minstreth>> CSRs (low word + high word).
-The maximum value is 64, the minimum value is 0. See section <<_machine_counter_and_timer_csrs>> for more information.
-This generic is only relevant if the `Zicntr` ISa extension is enabled (<<_cpu_extension_riscv_zicntr>>).
-Note: configurations with a counter width of less than 64 bits do not comply to the RISC-V specs.
-|======
-
-
 :sectnums!:
 ===== _CPU_IPB_ENTRIES_
 

docs/userguide/application_specific_configuration.adoc

@@ -52,9 +52,9 @@ and DMEM memories.
 * Use the _embedded_ RISC-V CPU architecture extension (`CPU_EXTENSION_RISCV_E`) to reduce block RAM utilization.
 * The compressed instructions extension (`CPU_EXTENSION_RISCV_C`) requires additional logic for the decoder but
 also reduces program code size by approximately 30%.
-* If not explicitly used/required, constrain the CPU's counter sizes: `CPU_CNT_WIDTH` for `[m]instret[h]`
-(number of instruction) and `[m]cycle[h]` (number of cycles) counters. You can even remove these counters
-by setting `CPU_CNT_WIDTH => 0` if they are not used at all (note, this is not RISC-V compliant).
+* If not explicitly used/required, exclude the CPU standart counters `[m]instret[h]`
+(number of instruction) and `[m]cycle[h]` (number of cycles) from synthesis by disabling the `Zicntr` ISA extension
+(note, this is not RISC-V compliant).
 * Reduce the CPU's prefetch buffer size (`CPU_IPB_ENTRIES`).
 * Map CPU shift operations to a small and iterative shifter unit (`FAST_SHIFT_EN => false`).
 * If you have unused DSP block available, you can map multiplication operations to those slices instead of
@@ -75,7 +75,7 @@ adds additional register stages to maintain critical path length. Obviously, thi
 In order to optimize for a minimal critical path (= maximum clock speed) the following points should be considered:
 
 * Complex CPU extensions (in terms of hardware requirements) should be avoided (examples: floating-point unit, physical memory protection).
-* Large carry chains (>32-bit) should be avoided (constrain CPU counter sizes: e.g. `CPU_CNT_WIDTH => 32` and `HPM_NUM_CNTS => 32`).
+* Large carry chains (>32-bit) should be avoided (i.e. constrain the HPM counter sizes via `HPM_CNT_WIDTH`).
 * If the target FPGA provides sufficient DSP resources, CPU multiplication operations can be mapped to DSP slices (`FAST_MUL_EN => true`)
 reducing LUT usage and critical path impact while also increasing overall performance.
 * Use the synchronous (registered) RX path configuration of the external memory interface (`MEM_EXT_ASYNC_RX => false`).

rtl/core/neorv32_cpu.vhd

@@ -67,7 +67,6 @@ entity neorv32_cpu is
     -- Extension Options --
     FAST_MUL_EN                  : boolean; -- use DSPs for M extension's multiplier
     FAST_SHIFT_EN                : boolean; -- use barrel shifter for shift operations
-    CPU_CNT_WIDTH                : natural; -- total width of CPU cycle and instret counters (0..64)
     CPU_IPB_ENTRIES              : natural; -- entries in instruction prefetch buffer, has to be a power of 2, min 2
     -- Physical Memory Protection (PMP) --
     PMP_NUM_REGIONS              : natural; -- number of regions (0..16)
@@ -181,10 +180,6 @@ begin
   -- CSR system --
   assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/privileged features available when <CPU_EXTENSION_RISCV_Zicsr> = false." severity warning;
 
-  -- CPU counters (cycle and instret) --
-  assert not ((CPU_EXTENSION_RISCV_Zicntr = true) and ((CPU_CNT_WIDTH < 0) or (CPU_CNT_WIDTH > 64))) report "NEORV32 CPU CONFIG ERROR! Invalid <CPU_CNT_WIDTH> configuration. Has to be 0..64." severity error;
-  assert not ((CPU_EXTENSION_RISCV_Zicntr = true) and (CPU_CNT_WIDTH < 64)) report "NEORV32 CPU CONFIG WARNING! Implementing CPU <cycle> and <instret> CSRs with reduced size (" & integer'image(CPU_CNT_WIDTH) & "-bit instead of 64-bit). This is not RISC-V compliant and might have unintended SW side effects." severity warning;
-
   -- U-extension requires Zicsr extension --
   assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
 
@@ -244,7 +239,6 @@ begin
     -- Tuning Options --
     FAST_MUL_EN                  => FAST_MUL_EN,                  -- use DSPs for M extension's multiplier
     FAST_SHIFT_EN                => FAST_SHIFT_EN,                -- use barrel shifter for shift operations
-    CPU_CNT_WIDTH                => CPU_CNT_WIDTH,                -- total width of CPU cycle and instret counters (0..64)
     CPU_IPB_ENTRIES              => CPU_IPB_ENTRIES,              -- entries is instruction prefetch buffer, has to be a power of 2, min 2
     -- Physical memory protection (PMP) --
     PMP_NUM_REGIONS              => PMP_NUM_REGIONS,              -- number of regions (0..16)