Add support for updating the contents of SYNC_ROM_REAL

[sgherbst]

Currently, updating ROM contents requires rebuilding the FPGA bitstream, which can be very time consuming. There are two ways to get around this problem:

1. Update the bitstream file directly with the new BRAM contents, then re-program the FPGA. This is possible using the data2mem tool (page 32 here). Since Vivado may sometimes use LUTs and FFs instead of a BRAM, the user would need to force BRAM inference for blocks that should be updatable in this manner. One advantage of this approach, however, is that there would be no additional resource utilization.
2. Wire control signals to the BRAM and update the BRAM contents while the FPGA is running. This could be done using either a single-port BRAM or a dual-port BRAM. This approach is less tool-dependent and doesn't require the user to force BRAM inference. However, it would increase resource utilization.

This task encompasses identifying which approach is more promising, and then implementing the required features in svreal (i.e., flag to force BRAM inference or port for writing BRAM contents).

[sgherbst]

This was addressed in PR #10