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Memory opt with word look up #466

Merged
merged 134 commits into from
Jul 17, 2023
Merged

Memory opt with word look up #466

merged 134 commits into from
Jul 17, 2023

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DreamWuGit
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@DreamWuGit DreamWuGit commented Apr 13, 2023 •
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spec refer to privacy-scaling-explorations/zkevm-specs#407
copy circuit design https://hackmd.io/_bMS2rvjQK23efyMkoHbkw
memory to memory design: https://hackmd.io/tuqJYr-DT3eqXvSM_6AHGQ?view

Refactor

  • extract common codes for state.gen_copy_steps_for_XXX @DreamWuGit
  • rethink some complex opcodes like bus-mapping::return_revert/sha3 @lispc

EVM circuit

  • add new memory word Op and calculate slot, shift
  • update fixed size memory lookup opcodes (mload/mstore/mstore8/calldataload)
  • update calldatacopy/codecopy/excodecopy
  • update logs/ sha3 / returndatacopy (WIP)
  • constrain mask, slot , shift relation, word equality. (@Aurel) https://app.asana.com/0/0/1204561543121039/f
  • update invalid_creation_code, return/revert/ create
  • fix CI issues, review if soundness problem ?
  • handle value_prev Memory opt update #541

state circuit

Copy circuit

  • add addr_slot ,word_index, value_wrod_rlc, mask columns and look up RW memory word when word_index = 31
  • lookup tx log byte to word (use addr_slot as address)
  • copy circuit tests for calldatacopy/codecopy/extcodecopy/logs/sha3 pass
  • review and update disabled constraints affected by memory word lookup and better way to change instead of disable : rows[0].addr + 1 == rows[2].addr, rows[0].rw_counter + rw_diff == rows[1].rw_counter , write value == read value， value_acc(2) == value_acc(0) * r + value(2), constraint etc.
  • add returndatacopy test in copy circuit side, originally missing.
  • constrain mask is bool & word_index [0--32] increase by 1
  • constrain addr_slot starts with zero and increase by 32 ?
  • fix copy circuit degree increase by 1
  • change copy circuit to reflect real/mask length such that evm gadget can use real copy length using real length in copy table lookup #565
  • refactor all type copy bytes using rlc_acc equality check(refactor all copy bytes using rlc_acc equality check  #604)

@DreamWuGit DreamWuGit changed the title add MemoryWordAddress gadget and todos Memory opt with word look up Apr 13, 2023
@DreamWuGit
fix mload buss mapping test
097b843
@DreamWuGit
add evm circuit with new memory word type and fix mstore circuit test…
67b0208 
… pass
@DreamWuGit
fix mload&mstor8 circuit
41b9bf9
@DreamWuGit
udpate error invalid creation code circuit
ce2e6c9
@DreamWuGit
update calldataload buss mapping
e022f88
@DreamWuGit
fix calldataload buss map test
103ee05
@DreamWuGit
update calldataload circuit&test pass
0e346d9
@DreamWuGit
update log* sha3 calldatacopy buss mapping tests
4fb963e
@DreamWuGit
add state circuit constraint for memory word tag
0765b97
@DreamWuGit
copy circuit buss mapping add mask field into copy event
f83a4bf
@DreamWuGit
copy circuit add value_wrod_rlc
ba676df
@DreamWuGit
add word_index into copy table and align calldata to word
fe2adfa
@DreamWuGit
merging
b8013f0
@DreamWuGit
fix word_index lt gate issue and move some columns
e973c0a
@DreamWuGit
fix memor word lookup & rw counter
6853367
@DreamWuGit
calldatacopy fix evm circuit root test
2feb995
@DreamWuGit
fix calldatacopy evm circuit internal test, memory offset overflow fail
c28f030
@DreamWuGit
fix codecopy bussmapping and copy circuit test pass
da083e9
@DreamWuGit
update codecopy evm circuit
6a69416
@DreamWuGit
update exrcodecopy and gen_copy_steps_for_log
6a7a745
@DreamWuGit
try log with byte lookup and refactor
dc3f5c2
@DreamWuGit
update log* with log byte to word and disable rows[0].addr + 1 == row…
ea76c6e 
…s[2].addr
@DreamWuGit
update sha3 copy circuit & evm circuit
3146962
naure and others added 4 commits July 13, 2023 13:05
@naure
word_rlc: introduce value_prev in copy circuit (#626)
830312d 
* word_rlc: introduce value_prev in copy circuit

* memory_opt_word_rlc: verify word RLCs

---------

Co-authored-by: Aurélien Nicolas <info@nau.re>
@naure
memory_opt_length: constrain length and mask (#628)
8122338 
* memory_opt_length: track both source and destination lengths. Simplify constraints

* memory_opt_length: constrain the shape of the mask

---------

Co-authored-by: Aurélien Nicolas <info@nau.re>
@naure
memory_opt_rwc: fix and simplify RW counter logic (#631)
212e12d 
* memory_opt_rwc: fix and simplify RW counter logic

* memory_opt_rwc: simplify CopyEvent rw functions

---------

Co-authored-by: Aurélien Nicolas <info@nau.re>
memory_opt: Prevent an event from spilling into the disabled rows.
9e559e5
@lispc
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lispc commented Jul 14, 2023

\b run testool

@zkevm-circuits-bots
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Succeed to run testool:
https://circuit-release.s3.us-west-2.amazonaws.com/testool/default.1689317364.600fda3.html

naure and others added 2 commits July 14, 2023 20:02
@naure
memory_opt_check_align: require aligned memory addresses in State (#634)
61902a0 
* memory_opt_check_align: require aligned memory addresses in State

* memory_opt_check_align: tests

---------

Co-authored-by: Aurélien Nicolas <info@nau.re>
@naure
Copy: remove LtChip (#635)
4eecece 
* memory_opt_rm_ltchip: replace LessThan with IsEqual

* memory_opt_rm_ltchip: support other rotations in IsEqualChip

* memory_opt_rm_ltchip: constrain is_pad from is_src_end_next

* memory_opt_rm_ltchip: remove the old chip

* memory_opt_rm_ltchip: add doc and assertion

---------

Co-authored-by: Aurélien Nicolas <info@nau.re>
naure and others added 8 commits July 14, 2023 18:02
@naure
memory_opt_readability: give a name to Rotations (#636)
cfbeb7f 
Co-authored-by: Aurélien Nicolas <info@nau.re>
memory_opt: organize variables and comments
3963a69
@naure
Copy Gadgets (#637)
72eaa1c 
* memory_opt_gadgets: move code into a function

* memory_opt_gadgets: move code into constrain_word_rlc()

* memory_opt_gadgets: move code into constrain_value_rlc()

* memory_opt_gadgets: move code into constrain_event_rlc_acc()

* memory_opt_gadgets: constrain_bytes_left

* memory_opt_gadgets: doc

* memory_opt_gadgets: move code into constrain_rw_counter. rustfmt works again!

* memory_opt_gadgets: constrain_forward_parameters and constrain_address

* memory_opt_gadgets: move code to constrain_mask()

* memory_opt_gadgets: move code to constrain_is_pad()

* memory_opt_gadgets: move code to constrain_non_pad_non_mask()

* memory_opt_gadgets: move code to constrain_first_last

* memory_opt_gadgets: constrain_masked_value and constrain_must_terminate

* memory_opt_gadgets: reorg is_pad and is_last

* memory_opt_gadgets: reorder gadgets to match the circuit

* memory_opt_gadgets: move code into constrain_tag. Done!

---------

Co-authored-by: Aurélien Nicolas <info@nau.re>
memory_opt: remove unnecessary is_event column
9474a74
@naure
memory_opt: remove duplicate code in CopyTable::assignments (#638)
33c0ccb 
Co-authored-by: Aurélien Nicolas <info@nau.re>
memory_opt: hide details of extend_at_least
1738239
@silathdiir
Avoid whole memory clone when generating copy steps (#629)
ad02341 
* Avoid whole memory clone for CODECOPY and EXTCODECOPY.

* Update

* Fix to extend memory as range(begin_slot, full_length), and update `src_addr_end`.

* Delete unused function `write_memory_words` in callop.

* Delete memory clone in callop.

* Fix lint.

* Delete memory clone in calldatacopy.

* Update returndatacopy, and extract to a common function.

* Fix lint.

* Update bytecode copy.

* Small fix.
Merge branch 'memory_opt' of github.com:scroll-tech/zkevm-circuits in…
9c8470b 
…to memory_opt
@lispc
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lispc commented Jul 17, 2023

\b run testool

@zkevm-circuits-bots
Copy link

Succeed to run testool:
https://circuit-release.s3.us-west-2.amazonaws.com/testool/default.1689585836.9c8470b.html

@lispc lispc merged commit fc6c8a2 into develop Jul 17, 2023
14 checks passed
@lispc lispc deleted the memory_opt branch July 17, 2023 12:36
@lispc lispc restored the memory_opt branch October 12, 2023 07:25
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@DreamWuGit @lightsing @silathdiir @lispc @naure