README.md

ECE369 Final Project

FPGA based implementation of a full-scale pipeline data path and hands-on tradeoff analysis on the joint effects of the hardware, software, and instruction set architecture design realms on processor performance.

Design and developed a five-stage pipeline processor for the MIPS 32-bit ISA.

Conduct post-routing functional verification

Final grade determined by 32 PRIVATE test cases.

Final Grade: 31/32