-
Notifications
You must be signed in to change notification settings - Fork 0
/
beta_CTL
97 lines (89 loc) · 2.98 KB
/
beta_CTL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
.subckt ctl reset irq Z id[31:26] ra2sel asel bsel wasel alufn[4:0] wdsel[1:0] pcsel[2:0] werf moe wr
Gctl memory vdd gnd gnd id[31:26] // one read port
+ xpcsel[2:0] xwasel asel bsel alufn[4:0] xwdsel[1:0] xwerf moe xwr
+ width=16 nlocations=64 contents=(
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0111000000000100//
+ 0b0000010000010110// LD 011000
+ 0b0000010000000001// ST 011001
+ 0b0111000000000100//
+ 0b0100000000000100//(JMP) 011011
+ 0b0000000000000100//(BEQ) 011100
+ 0b0010000000000100//(BNE) 011101
+ 0b0111000000000100//
+ 0b0000101101010110//(LDR) 011111
+ 0b0000000000001100// ADD 100000
+ 0b0000000000101100// SUB 100001
+ 0b0000000001001100// MUL* 100010
+ 0b0111000000000100//0b0000000alufn01100// DIV* 100011
+ 0b0000000010101100// CMPEQ 100100
+ 0b0000000011101100// CMPLT 100101
+ 0b0000000110101100// CMPLE 100110
+ 0b0111000000000100//
+ 0b0000001100001100// AND 101000
+ 0b0000001111001100// OR 101001
+ 0b0000001011001100// XOR 101010
+ 0b0000001100101100// XNOR 101011
+ 0b0000000100001100// SHL 101100
+ 0b0000000100101100// SHR 101101
+ 0b0000000101101100// SRA 101110
+ 0b0111000000000100//
+ 0b0000010000001100// ADDC 110000
+ 0b0000010000101100// SUBC 110001
+ 0b0000010001001100// MULC* 110010
+ 0b0111000000000100//0b0000001alufn01100// DIVC* 110011
+ 0b0000010010101100// CMPEQC 110100
+ 0b0000010011101100// CMPLTC 110101
+ 0b0000010110101100// CMPLEC 110110
+ 0b0111000000000100//
+ 0b0000011100001100// ANDC 111000
+ 0b0000011111001100// ORC 111001
+ 0b0000011011001100// XORC 111010
+ 0b0000011100101100// XNORC 110011
+ 0b0000010100001100// SHLC 110100
+ 0b0000010100101100// SHRC 110101
+ 0b0000010101101100// SRAC 110110
+ 0b0111000000000100//
+ )
Xwrmux mux2 reset xwr gnd xxwr
//adding z bits into pcsel via logic, not rom:
//use logic gates to find if a BE instruction
Xandpc and3 id[30:28] pcand
Xnorpc nor2 id[31] id[27] pcnor
Xisbe and2 pcand pcnor isbe
//determine the appropriate z signal
Xnotz nor2 gnd Z notZ
Xmuxzsig mux2 id[26] Z notZ zsig
Xmuxbe mux2 isbe#3 xpcsel[2:0] gnd#2 zsig x2pcsel[2:0]
//mux for interrupts
XmuxPCSEL mux2 irq#3 x2pcsel[2:0] vdd gnd#2 pcsel[2:0]
XorWASEL or2 xwasel irq wasel
XorWERF or2 xwerf irq werf
XmuxWDSEL mux2 irq#2 xwdsel[1:0] gnd#2 wdsel[1:0]
XmuxWR mux2 irq xxwr gnd wr
//determine ra2sel via logic
//note that ra2sel is 1 for st, 0 for OP, and -- for all else
Xinv inverter id[31] ra2sel
.ends