Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

RISC-V -mcmodel=medium #59802

Closed
fintelia opened this issue Apr 8, 2019 · 6 comments · Fixed by #62281
Closed

RISC-V -mcmodel=medium #59802

fintelia opened this issue Apr 8, 2019 · 6 comments · Fixed by #62281
Labels
A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. C-feature-request Category: A feature request, i.e: not implemented / a PR. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.

Comments

@fintelia
Copy link
Contributor

fintelia commented Apr 8, 2019

LLVM recently added some support for mcmodel=medium (which is equivalent to GCC's mcmodel=medany). I believe that this means that it is now possible to cherry pick the relevant commits and expose support from Rust.

See also: rust-embedded/wg/issues/218
@jonas-schievink jonas-schievink added A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. C-feature-request Category: A feature request, i.e: not implemented / a PR. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue. labels Apr 8, 2019
@laanwj
Copy link

laanwj commented Apr 16, 2019

great !
would be useful for me as well: Kendryte K210 expects code to run from fixed address 80000000, so medlow relocations get truncated

@arunthomas
Copy link

Greetings from Oxidize!

It'd be great if someone could bump LLVM, so we can start adding support for Linux/RV64 targets. It was suggested @alexcrichton might be the person to ping about this.

@asb Is there a specific LLVM version you would recommend? I assume we want at least llvm/llvm-project@da20f5c, but I imagine there may be other upstream fixes that are needed.

Thanks!

CCing @Disasm @jamesmunns

@fintelia
Copy link
Contributor Author

fintelia commented Apr 27, 2019 •
edited
Loading

@arunthomas Rust can already target bare metal Rv64 (with the riscv64imac-unknown-none-elf target). What is missing is the ability to place the code/symbols* at locations outside the range [-2GB, 2GB]. That isn't too much of an issue for writing supervisor mode code which can just configure the MMU to map those addresses to point to RAM, but machine mode can't pick the memory layout of the board it runs on.

*You actually can get away with having code outside this range as long as there aren't any indirect jumps or static variables there. It is very restrictive and inconvenient, but you might be able to get away with it for a small amount of code.

@Disasm
Copy link
Contributor

Disasm commented Apr 27, 2019

I also really want these patches to be merged. I've already tried to merge upstream branch as well as to deduce a cherry-pick-able set of commits but failed in both cases. Because of that, I can't tell whether these patches will fix the issue or not. At the moment I'm stuck waiting for help. I'm ready to give it another try, but I need some guidance. Maybe @alexcrichton or @asb could help me?

@alexcrichton
Copy link
Member

There's instructions/rationale about updating LLVM hosted at https://rust-lang.github.io/rustc-guide/codegen/updating-llvm.html. Instructions are slightly out of date but I'll send a PR to fix them.

@WRansohoff WRansohoff mentioned this issue Jun 8, 2019
Closed
@Disasm
Copy link
Contributor

Disasm commented Jun 23, 2019

(Current status) This patch arrived in LLVM: llvm/llvm-project@a524036
Now LLVM is able to generate pc-relative address load instructions for global variables and functions.

@fintelia fintelia mentioned this issue Jun 26, 2019
Closed
This was referenced Jun 30, 2019
Merged
Merged
Centril added a commit to Centril/rust that referenced this issue Jul 6, 2019
@Centril
Rollup merge of rust-lang#62281 - Disasm:riscv-pic, r=nagisa
5c6b58e 
Add support for pc-relative addressing on 64-bit RISC-V

These changes allow Rust to generate position-independent code on `riscv64` targets with code model `medium`.

Closes: rust-lang#59802
See also: rust-embedded/riscv-rt#25, rust-embedded/wg#218
bors added a commit that referenced this issue Jul 7, 2019
@bors
Auto merge of #62281 - Disasm:riscv-pic, r=nagisa
4393768 
Add support for pc-relative addressing on 64-bit RISC-V

These changes allow Rust to generate position-independent code on `riscv64` targets with code model `medium`.

Closes: #59802
See also: rust-embedded/riscv-rt#25, rust-embedded/wg#218
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. C-feature-request Category: A feature request, i.e: not implemented / a PR. O-riscv Target: RISC-V architecture T-compiler Relevant to the compiler team, which will review and decide on the PR/issue.
Projects
None yet
Milestone
No milestone
Development

Successfully merging a pull request may close this issue.

Add support for pc-relative addressing on 64-bit RISC-V Disasm/rust
6 participants
@arunthomas @alexcrichton @laanwj @Disasm @jonas-schievink @fintelia