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CORE-V: Support ALU Extension #2

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Commits on Sep 1, 2023

  1. RISC-V: Add support for XCValu extension in CV32E40P

    Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
    
    Contributors:
        Mary Bennett
        Nandni Jamnadas
        Pietra Ferreira
        Charlie Keaney
        Jessica Mills
        Craig Blackmore
        Simon Cook
        Jeremy Bennett
    
    bfd/ChangeLog:
    
    	* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu`
              instruction class.
    	(riscv_multi_subset_supports_ext): Likewise.
    
    gas/ChangeLog:
    
    	* config/tc-riscv.c (validate_riscv_insn): Added the necessary
              operands for the extension.
    	(riscv_ip): Likewise.
    	* doc/c-riscv.texi: Noted XCValu as an additional ISA extension
              for CORE-V.
    	* testsuite/gas/riscv/cv-alu-boundaries.d: New test.
    	* testsuite/gas/riscv/cv-alu-boundaries.l: New test.
    	* testsuite/gas/riscv/cv-alu-boundaries.s: New test.
    	* testsuite/gas/riscv/cv-alu-fail-march.d: New test.
    	* testsuite/gas/riscv/cv-alu-fail-march.l: New test.
    	* testsuite/gas/riscv/cv-alu-fail-march.s: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test.
    	* testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test.
    	* testsuite/gas/riscv/cv-alu-insns.d: New test.
    	* testsuite/gas/riscv/cv-alu-insns.s: New test.
    
    opcodes/ChangeLog:
    
    	* riscv-dis.c (print_insn_args): Disassemble xcb operand.
    	* riscv-opc.c: Defined the MASK and added XCValu instructions.
    
    include/ChangeLog:
    
    	* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
              for XCValu.
    	* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
              for XCValu.
    	(enum riscv_insn_class): Added the XCValu instruction class.
    jessicamills authored and pietraferreira committed Sep 1, 2023
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