Refactoring, mainly the switch statements

pietraferreira · Aug 31, 2023 · df12b75 · df12b75
1 parent 1fb8815
commit df12b75
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Showing 5 changed files with 46 additions and 51 deletions.
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
@@ -1361,7 +1361,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadsync",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   /* XVentanaCondOps: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf */
   {"xventanacondops",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
-  /* CORE-V encoding spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
+  /* CORE-V ISA extension spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
   {"xcvalu",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
@@ -1475,17 +1475,18 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	    {
 	      /* Vendor-specific (CORE-V) operands.  */
 	      case 'c':
-		if (oparg[1] == '3')
+		switch(*++oparg)
 		  {
-		    /* ls3 [4:0] */
-		    used_bits |= ENCODE_CV_IS3_UIMM5(-1U);
-		    ++oparg; break;
-		  }
-		else if (oparg[1] == '2')
-		  {
-		    /* ls2 [4:0] */
-		    used_bits |= ENCODE_CV_IS2_UIMM5(-1U);
-		    ++oparg; break;
+		    case '2':
+		      /* ls2 [4:0] */
+		      used_bits |= ENCODE_CV_IS2_UIMM5(-1U);
+		      break;
+		    case '3':
+		      /* ls3 [4:0] */
+		      used_bits |= ENCODE_CV_IS3_UIMM5(-1U);
+		      break;
+		    default:
+		      goto unknown_validate_operand;
 		  }
 		break;
 	      default:
@@ -3697,29 +3698,26 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		{
 		  /* Vendor-specific (CORE-V) operands.  */
 		  case 'c':
-		    if (oparg[1] == '3')
-		      {
-			my_getExpression (imm_expr, asarg);
-			check_absolute_expr (ip, imm_expr, FALSE);
-			asarg = expr_parse_end;
-			if (imm_expr->X_add_number<0 || imm_expr->X_add_number>31) break;
-			ip->insn_opcode |= ENCODE_CV_IS3_UIMM5 (imm_expr->X_add_number);
-			++oparg;
-		      }
-		    else if (oparg[1] == '2')
+		    switch(*++oparg)
 		      {
-			my_getExpression (imm_expr, asarg);
-			check_absolute_expr (ip, imm_expr, FALSE);
-			asarg = expr_parse_end;
-			if (imm_expr->X_add_number<0 || imm_expr->X_add_number>31) break;
-			ip->insn_opcode |= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);
-			++oparg;
+			case '2':
+			  my_getExpression (imm_expr, asarg);
+			  check_absolute_expr (ip, imm_expr, FALSE);
+			  asarg = expr_parse_end;
+			  if (imm_expr->X_add_number<0 || imm_expr->X_add_number>31) break;
+			  ip->insn_opcode |= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);
+			  continue;
+			case '3':
+			  my_getExpression (imm_expr, asarg);
+			  check_absolute_expr (ip, imm_expr, FALSE);
+			  asarg = expr_parse_end;
+			  if (imm_expr->X_add_number<0 || imm_expr->X_add_number>31) break;
+			  ip->insn_opcode |= ENCODE_CV_IS3_UIMM5 (imm_expr->X_add_number);
+			  continue;
+			default:
+			  goto unknown_riscv_ip_operand;
 		      }
-		    else
-		      {
-			goto unknown_riscv_ip_operand;
-		      }
-		    continue;
+		    break;
 		  default:
 		    goto unknown_riscv_ip_operand;
 		}

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
@@ -3024,7 +3024,6 @@
 #define CSR_VTYPE 0xc21
 #define CSR_VLENB 0xc22
 #endif /* RISCV_ENCODING_H */
-
 #ifdef DECLARE_INSN
 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
 DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
@@ -113,10 +113,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define EXTRACT_ZCB_HALFWORD_UIMM(x) \
   (RV_X(x, 5, 1) << 1)
 /* Vendor-specific (CORE-V) extract macros.  */
-#define EXTRACT_CV_IS3_UIMM5(x) \
-  (RV_X(x, 25, 5))
 #define EXTRACT_CV_IS2_UIMM5(x) \
   (RV_X(x, 20, 5))
+#define EXTRACT_CV_IS3_UIMM5(x) \
+  (RV_X(x, 25, 5))
 
 #define ENCODE_ITYPE_IMM(x) \
   (RV_X(x, 0, 12) << 20)
@@ -169,10 +169,10 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define ENCODE_ZCB_HALFWORD_UIMM(x) \
   (RV_X(x, 1, 1) << 5)
 /* Vendor-specific (CORE-V) encode macros.  */
-#define ENCODE_CV_IS3_UIMM5(x) \
-  (RV_X(x, 0, 5) << 25)
 #define ENCODE_CV_IS2_UIMM5(x) \
   (RV_X(x, 0, 5) << 20)
+#define ENCODE_CV_IS3_UIMM5(x) \
+  (RV_X(x, 0, 5) << 25)
 
 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
@@ -429,25 +429,23 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	    print (info->stream, dis_style_immediate, "0");
 	  break;
 
-	/* CORE-V Specific.  */
-	case 'x':
+	case 'x': /* Vendor-specific operands.  */
 	  switch (*++oparg)
 	    {
+	    /* Vendor-specific (CORE-V) operands.  */
 	    case 'c':
-	      if (oparg[1] == '3')
+	      switch(*++oparg)
 		{
-		  print (info->stream, dis_style_immediate, "%d", 
-			 ((int) EXTRACT_CV_IS3_UIMM5 (l)));
-		  ++oparg;
-		  break;
-		}
-	      else if (oparg[1] == '2')
-		{
-		  print (info->stream, dis_style_immediate, "%d", 
-			 ((int) EXTRACT_CV_IS2_UIMM5 (l)));
-		  ++oparg;
-		  break;
+		  case '2':
+		    print (info->stream, dis_style_immediate, "%d", 
+			   ((int) EXTRACT_CV_IS2_UIMM5 (l)));
+		    break;
+		  case '3':
+		    print (info->stream, dis_style_immediate, "%d", 
+			   ((int) EXTRACT_CV_IS3_UIMM5 (l)));
+		    break;
 		}
+	      break;
 	    }
 	  break;