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Suggested fixes, mainly formatting
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@pietraferreira
pietraferreira committed Aug 30, 2023
1 parent 8bafd89 commit 5bc0bd4
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Showing 6 changed files with 86 additions and 87 deletions.
11 changes: 6 additions & 5 deletions bfd/elfxx-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1361,7 +1361,8 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
/* XVentanaCondOps: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf */
{"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
/* CORE-V encoding spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html */
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};

Expand Down Expand Up @@ -2468,8 +2469,6 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return (riscv_subset_supports (rps, "zfh")
|| riscv_subset_supports (rps, "zvfh"))
&& riscv_subset_supports (rps, "zfa");
case INSN_CLASS_CV_ALU:
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_ZBA:
return riscv_subset_supports (rps, "zba");
case INSN_CLASS_ZBB:
Expand Down Expand Up @@ -2542,6 +2541,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
return riscv_subset_supports (rps, "h");
case INSN_CLASS_XCVALU:
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XTHEADBA:
return riscv_subset_supports (rps, "xtheadba");
case INSN_CLASS_XTHEADBB:
Expand Down Expand Up @@ -2722,8 +2723,6 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
}
else
return _("zfh' or `zvfh");
case INSN_CLASS_CV_ALU:
return "xcvalu";
case INSN_CLASS_ZBA:
return "zba";
case INSN_CLASS_ZBB:
Expand Down Expand Up @@ -2784,6 +2783,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "svinval";
case INSN_CLASS_H:
return _("h");
case INSN_CLASS_XCVALU:
return "xcvalu";
case INSN_CLASS_XTHEADBA:
return "xtheadba";
case INSN_CLASS_XTHEADBB:
Expand Down
2 changes: 1 addition & 1 deletion gas/config/tc-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1357,7 +1357,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case 'A': break; /* Macro operand, must be symbol. */
case 'B': break; /* Macro operand, must be symbol or constant. */
case 'b': /* CORE-V Specific. */
case 'b': /* Vendor-specific (CORE-V) Xcvalu. */
if (oparg[1] == '3')
{
/* ls3 [4:0] */
Expand Down
6 changes: 6 additions & 0 deletions gas/doc/c-riscv.texi
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Original file line number Diff line number Diff line change
Expand Up @@ -753,6 +753,12 @@ extensions supported and provides the location of their
publicly-released documentation:

@table @r
@item Xcvalu

The Xcvalu extension provides instructions for general ALU operations.

It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}

@item XTheadBa
The XTheadBa extension provides instructions for address calculations.

Expand Down
73 changes: 35 additions & 38 deletions include/opcode/riscv-opc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2342,6 +2342,41 @@
#define MASK_TH_REVW 0xfff0707f
#define MATCH_TH_TSTNBZ 0x8000100b
#define MASK_TH_TSTNBZ 0xfff0707f
/* Vendor-specific (CORE-V) Xcvalu instructions. */
#define MATCH_CV_ABS 0x5000302b
#define MASK_CV_ABS 0xfff0707f
#define MATCH_CV_SLET 0x5200302b
#define MASK_CV_SLET 0xfe00707f
#define MATCH_CV_SLETU 0x5400302b
#define MATCH_CV_MIN 0x5600302b
#define MATCH_CV_MINU 0x5800302b
#define MATCH_CV_MAX 0x5a00302b
#define MATCH_CV_MAXU 0x5c00302b
#define MATCH_CV_EXTHS 0x6000302b
#define MATCH_CV_EXTHZ 0x6200302b
#define MATCH_CV_EXTBS 0x6400302b
#define MATCH_CV_EXTBZ 0x6600302b
#define MATCH_CV_CLIP 0x7000302b
#define MATCH_CV_CLIPU 0x7200302b
#define MATCH_CV_CLIPR 0x7400302b
#define MATCH_CV_CLIPUR 0x7600302b
#define MATCH_CV_ADDNR 0x8000302b
#define MATCH_CV_ADDUNR 0x8200302b
#define MATCH_CV_ADDRNR 0x8400302b
#define MATCH_CV_ADDURNR 0x8600302b
#define MATCH_CV_SUBNR 0x8800302b
#define MATCH_CV_SUBUNR 0x8a00302b
#define MATCH_CV_SUBRNR 0x8c00302b
#define MATCH_CV_SUBURNR 0x8e00302b
#define MATCH_CV_ADDN 0x205b
#define MASK_CV_ADDN 0xc000707f
#define MATCH_CV_ADDUN 0x4000205b
#define MATCH_CV_ADDRN 0x8000205b
#define MATCH_CV_ADDURN 0xc000205b
#define MATCH_CV_SUBN 0x305b
#define MATCH_CV_SUBUN 0x4000305b
#define MATCH_CV_SUBRN 0x8000305b
#define MATCH_CV_SUBURN 0xc000305b
/* Vendor-specific (T-Head) XTheadBs instructions. */
#define MATCH_TH_TST 0x8800100b
#define MASK_TH_TST 0xfc00707f
Expand Down Expand Up @@ -2990,44 +3025,6 @@
#define CSR_VLENB 0xc22
#endif /* RISCV_ENCODING_H */

/* CORE-V Specific Instructions */
/* General ALU operations */
#define MATCH_CV_ABS 0x5000302b
#define MATCH_CV_SLET 0x5200302b
#define MATCH_CV_SLETU 0x5400302b
#define MATCH_CV_MIN 0x5600302b
#define MATCH_CV_MINU 0x5800302b
#define MATCH_CV_MAX 0x5a00302b
#define MATCH_CV_MAXU 0x5c00302b
#define MATCH_CV_EXTHS 0x6000302b
#define MATCH_CV_EXTHZ 0x6200302b
#define MATCH_CV_EXTBS 0x6400302b
#define MATCH_CV_EXTBZ 0x6600302b
#define MATCH_CV_CLIP 0x7000302b
#define MATCH_CV_CLIPU 0x7200302b
#define MATCH_CV_CLIPR 0x7400302b
#define MATCH_CV_CLIPUR 0x7600302b
#define MATCH_CV_ADDNR 0x8000302b
#define MATCH_CV_ADDUNR 0x8200302b
#define MATCH_CV_ADDRNR 0x8400302b
#define MATCH_CV_ADDURNR 0x8600302b
#define MATCH_CV_SUBNR 0x8800302b
#define MATCH_CV_SUBUNR 0x8a00302b
#define MATCH_CV_SUBRNR 0x8c00302b
#define MATCH_CV_SUBURNR 0x8e00302b
#define MATCH_CV_ADDN 0x205b
#define MATCH_CV_ADDUN 0x4000205b
#define MATCH_CV_ADDRN 0x8000205b
#define MATCH_CV_ADDURN 0xc000205b
#define MATCH_CV_SUBN 0x305b
#define MATCH_CV_SUBUN 0x4000305b
#define MATCH_CV_SUBRN 0x8000305b
#define MATCH_CV_SUBURN 0xc000305b

#define MASK_CV_ABS 0xfff0707f
#define MASK_CV_SLET 0xfe00707f
#define MASK_CV_ADDN 0xc000707f

#ifdef DECLARE_INSN
DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
Expand Down
8 changes: 3 additions & 5 deletions include/opcode/riscv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -112,8 +112,7 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
#define EXTRACT_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 5, 1) << 1)

/* CORE-V Specific. */
/* Vendor-specific (CORE-V) Xcvalu extract macros. */
#define EXTRACT_CV_L_UIMM5(x) \
(RV_X(x, 25, 5))
#define EXTRACT_CV_I_UIMM5(x) \
Expand Down Expand Up @@ -169,8 +168,7 @@ static inline unsigned int riscv_insn_length (insn_t insn)
((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
#define ENCODE_ZCB_HALFWORD_UIMM(x) \
(RV_X(x, 1, 1) << 5)

/* CORE-V Specific. */
/* Vendor-specific (CORE-V) Xcvalu encode macros. */
#define ENCODE_CV_L_UIMM5(x) \
(RV_X(x, 0, 5) << 25)
#define ENCODE_CV_I_UIMM5(x) \
Expand Down Expand Up @@ -422,7 +420,6 @@ enum riscv_insn_class
INSN_CLASS_Q_AND_ZFA,
INSN_CLASS_ZFH_AND_ZFA,
INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA,
INSN_CLASS_CV_ALU,
INSN_CLASS_ZBA,
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
Expand Down Expand Up @@ -456,6 +453,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOP,
INSN_CLASS_ZICBOZ,
INSN_CLASS_H,
INSN_CLASS_XCVALU,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,
Expand Down
73 changes: 35 additions & 38 deletions opcodes/riscv-opc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2039,6 +2039,41 @@ const struct riscv_opcode riscv_opcodes[] =
{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },

/* Vendor-specific (CORE-V) Xcvalu instructions. */
{"cv.abs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_ABS, MASK_CV_ABS, match_opcode, 0},
{"cv.exths", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHS, MASK_CV_ABS, match_opcode, 0},
{"cv.exthz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTHZ, MASK_CV_ABS, match_opcode, 0},
{"cv.extbs", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBS, MASK_CV_ABS, match_opcode, 0},
{"cv.extbz", 0, INSN_CLASS_XCVALU, "d,s", MATCH_CV_EXTBZ, MASK_CV_ABS, match_opcode, 0},
{"cv.sle", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET, MASK_CV_SLET, match_opcode, 0},
{"cv.slet", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLET, MASK_CV_SLET, match_opcode, INSN_ALIAS},
{"cv.sleu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU, MASK_CV_SLET, match_opcode, 0},
{"cv.sletu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SLETU, MASK_CV_SLET, match_opcode, INSN_ALIAS},
{"cv.min", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MIN, MASK_CV_SLET, match_opcode, 0},
{"cv.minu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MINU, MASK_CV_SLET, match_opcode, 0},
{"cv.max", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAX, MASK_CV_SLET, match_opcode, 0},
{"cv.maxu", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_MAXU, MASK_CV_SLET, match_opcode, 0},
{"cv.clip", 0, INSN_CLASS_XCVALU, "d,s,bi", MATCH_CV_CLIP, MASK_CV_SLET, match_opcode, 0},
{"cv.clipu", 0, INSN_CLASS_XCVALU, "d,s,bi", MATCH_CV_CLIPU, MASK_CV_SLET, match_opcode, 0},
{"cv.clipr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPR, MASK_CV_SLET, match_opcode, 0},
{"cv.clipur", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_CLIPUR, MASK_CV_SLET, match_opcode, 0},
{"cv.addn", 0, INSN_CLASS_XCVALU, "d,s,t,b3", MATCH_CV_ADDN, MASK_CV_ADDN, match_opcode, 0},
{"cv.addun", 0, INSN_CLASS_XCVALU, "d,s,t,b3", MATCH_CV_ADDUN, MASK_CV_ADDN, match_opcode, 0},
{"cv.addunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDUNR, MASK_CV_SLET, match_opcode, 0},
{"cv.addrn", 0, INSN_CLASS_XCVALU, "d,s,t,b3", MATCH_CV_ADDRN, MASK_CV_ADDN, match_opcode, 0},
{"cv.addurn", 0, INSN_CLASS_XCVALU, "d,s,t,b3", MATCH_CV_ADDURN, MASK_CV_ADDN, match_opcode, 0},
{"cv.addnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDNR, MASK_CV_SLET, match_opcode, 0},
{"cv.addrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDRNR, MASK_CV_SLET, match_opcode, 0},
{"cv.addurnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_ADDURNR, MASK_CV_SLET, match_opcode, 0},
{"cv.subn", 0, INSN_CLASS_XCVALU, "d,s,t,b3", MATCH_CV_SUBN, MASK_CV_ADDN, match_opcode, 0},
{"cv.subun", 0, INSN_CLASS_XCVALU, "d,s,t,b3", MATCH_CV_SUBUN, MASK_CV_ADDN, match_opcode, 0},
{"cv.subrn", 0, INSN_CLASS_XCVALU, "d,s,t,b3", MATCH_CV_SUBRN, MASK_CV_ADDN, match_opcode, 0},
{"cv.suburn", 0, INSN_CLASS_XCVALU, "d,s,t,b3", MATCH_CV_SUBURN, MASK_CV_ADDN, match_opcode, 0},
{"cv.subnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBNR, MASK_CV_SLET, match_opcode, 0},
{"cv.subunr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBUNR, MASK_CV_SLET, match_opcode, 0},
{"cv.subrnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBRNR, MASK_CV_SLET, match_opcode, 0},
{"cv.suburnr", 0, INSN_CLASS_XCVALU, "d,s,t", MATCH_CV_SUBURNR, MASK_CV_SLET, match_opcode, 0},

/* Vendor-specific (T-Head) XTheadBa instructions. */
{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},

Expand Down Expand Up @@ -2177,44 +2212,6 @@ const struct riscv_opcode riscv_opcodes[] =
{"vt.maskc", 0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
{"vt.maskcn", 0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },

/* CORE-V Specific Opcodes. */
/* General ALU operations */
{"cv.abs", 0, INSN_CLASS_CV_ALU, "d,s", MATCH_CV_ABS, MASK_CV_ABS, match_opcode, 0},
{"cv.exths", 0, INSN_CLASS_CV_ALU, "d,s", MATCH_CV_EXTHS, MASK_CV_ABS, match_opcode, 0},
{"cv.exthz", 0, INSN_CLASS_CV_ALU, "d,s", MATCH_CV_EXTHZ, MASK_CV_ABS, match_opcode, 0},
{"cv.extbs", 0, INSN_CLASS_CV_ALU, "d,s", MATCH_CV_EXTBS, MASK_CV_ABS, match_opcode, 0},
{"cv.extbz", 0, INSN_CLASS_CV_ALU, "d,s", MATCH_CV_EXTBZ, MASK_CV_ABS, match_opcode, 0},
{"cv.sle", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_SLET, MASK_CV_SLET, match_opcode, 0},
{"cv.slet", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_SLET, MASK_CV_SLET, match_opcode, INSN_ALIAS},
{"cv.sleu", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_SLETU, MASK_CV_SLET, match_opcode, 0},
{"cv.sletu", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_SLETU, MASK_CV_SLET, match_opcode, INSN_ALIAS},
{"cv.min", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_MIN, MASK_CV_SLET, match_opcode, 0},
{"cv.minu", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_MINU, MASK_CV_SLET, match_opcode, 0},
{"cv.max", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_MAX, MASK_CV_SLET, match_opcode, 0},
{"cv.maxu", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_MAXU, MASK_CV_SLET, match_opcode, 0},
{"cv.clip", 0, INSN_CLASS_CV_ALU, "d,s,bi", MATCH_CV_CLIP, MASK_CV_SLET, match_opcode, 0},
{"cv.clipu", 0, INSN_CLASS_CV_ALU, "d,s,bi", MATCH_CV_CLIPU, MASK_CV_SLET, match_opcode, 0},
{"cv.clipr", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_CLIPR, MASK_CV_SLET, match_opcode, 0},
{"cv.clipur", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_CLIPUR, MASK_CV_SLET, match_opcode, 0},
{"cv.addn", 0, INSN_CLASS_CV_ALU, "d,s,t,b3", MATCH_CV_ADDN, MASK_CV_ADDN, match_opcode, 0},
{"cv.addun", 0, INSN_CLASS_CV_ALU, "d,s,t,b3", MATCH_CV_ADDUN, MASK_CV_ADDN, match_opcode, 0},
{"cv.addunr", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_ADDUNR, MASK_CV_SLET, match_opcode, 0},
{"cv.addrn", 0, INSN_CLASS_CV_ALU, "d,s,t,b3", MATCH_CV_ADDRN, MASK_CV_ADDN, match_opcode, 0},
{"cv.addurn", 0, INSN_CLASS_CV_ALU, "d,s,t,b3", MATCH_CV_ADDURN, MASK_CV_ADDN, match_opcode, 0},
{"cv.addnr", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_ADDNR, MASK_CV_SLET, match_opcode, 0},
{"cv.addrnr", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_ADDRNR, MASK_CV_SLET, match_opcode, 0},
{"cv.addurnr", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_ADDURNR, MASK_CV_SLET, match_opcode, 0},
{"cv.subn", 0, INSN_CLASS_CV_ALU, "d,s,t,b3", MATCH_CV_SUBN, MASK_CV_ADDN, match_opcode, 0},
{"cv.subun", 0, INSN_CLASS_CV_ALU, "d,s,t,b3", MATCH_CV_SUBUN, MASK_CV_ADDN, match_opcode, 0},
{"cv.subrn", 0, INSN_CLASS_CV_ALU, "d,s,t,b3", MATCH_CV_SUBRN, MASK_CV_ADDN, match_opcode, 0},
{"cv.suburn", 0, INSN_CLASS_CV_ALU, "d,s,t,b3", MATCH_CV_SUBURN, MASK_CV_ADDN, match_opcode, 0},
{"cv.subnr", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_SUBNR, MASK_CV_SLET, match_opcode, 0},
{"cv.subunr", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_SUBUNR, MASK_CV_SLET, match_opcode, 0},
{"cv.subrnr", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_SUBRNR, MASK_CV_SLET, match_opcode, 0},
{"cv.suburnr", 0, INSN_CLASS_CV_ALU, "d,s,t", MATCH_CV_SUBURNR, MASK_CV_SLET, match_opcode, 0},

/* END OF CORE-V */

/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
};
Expand Down

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