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vivado_4772.backup.log
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#-----------------------------------------------------------
# Vivado v2022.1 (64-bit)
# SW Build 3526262 on Mon Apr 18 15:48:16 MDT 2022
# IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
# Start of session at: Mon Jan 9 23:36:19 2023
# Process ID: 4772
# Current directory: C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent13840 C:\Users\ozand\Desktop\3017 Project\CSE3017_PROJECT\CSE3017_PROJECT.xpr
# Log file: C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/vivado.log
# Journal file: C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT\vivado.jou
# Running On: DESKTOP-AFJAC9R, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 17010 MB
#-----------------------------------------------------------
start_gui
open_project {C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.xpr}
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es_revb:part0:1.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120_revb/es/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at D:/Xilinix/Vivado/2022.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.gen/sources_1'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinix/Vivado/2022.1/data/ip'.
open_project: Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1209.238 ; gain = 0.000
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'FIR_TB'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Xilinix/Vivado/2022.1/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'FIR_TB' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim/signal.data'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj FIR_TB_vlog.prj"
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot FIR_TB_behav xil_defaultlib.FIR_TB xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinix/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot FIR_TB_behav xil_defaultlib.FIR_TB xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:21]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:22]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:23]
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "FIR_TB_behav -key {Behavioral:sim_1:Functional:FIR_TB} -tclbatch {FIR_TB.tcl} -view {{C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config {C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}
source FIR_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'FIR_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 1209.238 ; gain = 0.000
run 2 us
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'FIR_TB'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Xilinix/Vivado/2022.1/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'FIR_TB' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim/signal.data'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj FIR_TB_vlog.prj"
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot FIR_TB_behav xil_defaultlib.FIR_TB xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinix/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot FIR_TB_behav xil_defaultlib.FIR_TB xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:21]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:22]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:23]
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "FIR_TB_behav -key {Behavioral:sim_1:Functional:FIR_TB} -tclbatch {FIR_TB.tcl} -view {{C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config {C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}
source FIR_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'FIR_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
run 2 us
save_wave_config {C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'FIR_TB'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Xilinix/Vivado/2022.1/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'FIR_TB' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim/signal.data'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj FIR_TB_vlog.prj"
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot FIR_TB_behav xil_defaultlib.FIR_TB xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinix/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot FIR_TB_behav xil_defaultlib.FIR_TB xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:21]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:22]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:23]
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "FIR_TB_behav -key {Behavioral:sim_1:Functional:FIR_TB} -tclbatch {FIR_TB.tcl} -view {{C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config {C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}
source FIR_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'FIR_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
set_property is_enabled false [get_files {{C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}}]
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'FIR_TB'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Xilinix/Vivado/2022.1/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'FIR_TB' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim/signal.data'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj FIR_TB_vlog.prj"
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot FIR_TB_behav xil_defaultlib.FIR_TB xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinix/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot FIR_TB_behav xil_defaultlib.FIR_TB xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:21]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:22]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:23]
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "FIR_TB_behav -key {Behavioral:sim_1:Functional:FIR_TB} -tclbatch {FIR_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
source FIR_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'FIR_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
run 2 us
run 2 us
set_property is_enabled true [get_files {{C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}}]
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'FIR_TB'
WARNING: [Vivado 12-13340] Unable to auto find GCC executables from simulator install path! (path not set)
WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'D:/Xilinix/Vivado/2022.1/tps/boost_1_72_0'
INFO: [SIM-utils-54] Inspecting design source files for 'FIR_TB' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim/signal.data'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj FIR_TB_vlog.prj"
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
"xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot FIR_TB_behav xil_defaultlib.FIR_TB xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2022.1
Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinix/Vivado/2022.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot FIR_TB_behav xil_defaultlib.FIR_TB xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:21]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:22]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'reset' [C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sources_1/new/FIR_Filter_Design.v:23]
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "FIR_TB_behav -key {Behavioral:sim_1:Functional:FIR_TB} -tclbatch {FIR_TB.tcl} -view {{C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
open_wave_config {C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}
source FIR_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'FIR_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
run 2 us
run 2 us
restart
INFO: [Simtcl 6-17] Simulation restarted
run 2 us
run 1 us
save_wave_config {C:/Users/ozand/Desktop/3017 Project/CSE3017_PROJECT/CSE3017_PROJECT.srcs/sim_1/imports/project_5/FIR_TB_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Mon Jan 9 23:46:25 2023...