RTL lint warnings

[tariqkurd-repo]

The E40P generates these lint warnings. They can all be fixed either by specifying the width of the constant (e.g. 1'b1 instead of 1) or casting to a user defined type.
e.g.

typedef logic [31:0] word_t;
word_t a,b,c;
always_comb a = (word_t)'(b+c);

removes the warning from the loss of carry bit

[MikeOpenHWGroup]

@davideschiavone, is this valid anymore? I do not see these lint warning with Verilator-4.100.

[pascalgouedo]

I don't see those warnings with Siemens EDA QuestaFormal as well.

But I do see them in Siemens EDA OneSpin as some Lint checks are launched before running assertions verifications:
XP_lint.log and XPF0_lint.log.

Totally depends of tools capabilities and setup.

But those warnings don't mean the design will be incorrectly implemented.
Would be better to have good coding style to prevent them but it is not worth the effort right now.

[pascalgouedo]

My feeling is that we can waive it.