RTL Code Coverage Hole in cv32e40p_controller module line 850 and lines 852 to 887

[pascalgouedo]

Component

Component:RTL

Issue Description

There is 1 branch and 3 conditions holes not covered on line 850 of cv32e40p_controller during all the simulation non-regressions.
This makes all lines from 852 to 887 uncovered as well.
The exactly same code in DECODE FSM state (lines 664 to 704) is totally covered by simulation tests.
But this one in DECODE_HWLOOP state is not covered at all.

Not sure this is not possible to have those branch/conditions covered as Hwloop debug single stepping prevents to go in DECODE_HWLOOP FSM state. Only 1 Hwloop instruction is executed at a time during single stepping but during normal Hwloop execution it is always going first to DECODE state and then to DECODE_HWLOOP one.
This seems unreachable branch and conditions but it needs to be proven formally.

As the sequence to come to this situation is extremely complex (program Hwloop CSRs, program debug registers to allow debug single step and then start to execute Hwloop body instructions), we have not been able to create all the tool constraints/assumes to prove this unreachability.