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Expanded cpp serial comm Verilog CI #30: Commit 7e36ee4 pushed by kir486680
January 24, 2024 20:29 43s comm_cpp
comm_cpp
January 24, 2024 20:29 43s
cpp comms Verilog CI #29: Commit 3b662d6 pushed by kir486680
January 24, 2024 03:02 32s comm_cpp
comm_cpp
January 24, 2024 03:02 32s
Merge pull request #6 from kir486680/fpga Verilog CI #28: Commit 7ce3a91 pushed by kir486680
January 18, 2024 15:35 37s master
master
January 18, 2024 15:35 37s
FPGA + Openlane Verilog CI #27: Pull request #6 opened by kir486680
January 18, 2024 15:35 30s fpga
fpga
January 18, 2024 15:35 30s
FPGA + Openlane Verilog CI #26: Commit a6801f3 pushed by kir486680
January 18, 2024 15:35 30s fpga
fpga
January 18, 2024 15:35 30s
Merge pull request #5 from kir486680/fpga Verilog CI #25: Commit 806d95b pushed by kir486680
January 3, 2024 20:14 30s master
master
January 3, 2024 20:14 30s
fpga implementation Verilog CI #24: Pull request #5 opened by kir486680
January 3, 2024 20:14 42s fpga
fpga
January 3, 2024 20:14 42s
fpga implementation Verilog CI #23: Commit 421776a pushed by kir486680
January 3, 2024 20:13 1m 12s fpga
fpga
January 3, 2024 20:13 1m 12s
Update README.md Verilog CI #22: Commit daa9d8a pushed by kir486680
December 22, 2023 14:44 27s master
master
December 22, 2023 14:44 27s
Merge pull request #4 from kir486680/block_mul Verilog CI #21: Commit f7d7c9e pushed by kir486680
December 22, 2023 14:41 31s master
master
December 22, 2023 14:41 31s
Block Mul Partially Works Verilog CI #20: Pull request #4 opened by kir486680
December 22, 2023 14:41 28s block_mul
block_mul
December 22, 2023 14:41 28s
Two cycle of matrix mul work Verilog CI #19: Commit ee6d150 pushed by kir486680
December 22, 2023 14:39 30s block_mul
block_mul
December 22, 2023 14:39 30s
one 2x2 mul cycle works Verilog CI #18: Commit 4ebde31 pushed by kir486680
December 21, 2023 21:29 30s block_mul
block_mul
December 21, 2023 21:29 30s
multiplication works? Verilog CI #17: Commit e3b66ff pushed by kir486680
December 21, 2023 19:20 30s block_mul
block_mul
December 21, 2023 19:20 30s
New Combinational blocks Verilog CI #16: Commit 91acb68 pushed by kir486680
November 26, 2023 20:33 34s block_mul
block_mul
November 26, 2023 20:33 34s
Think my for loops are broken Verilog CI #15: Commit 640334d pushed by kir486680
November 26, 2023 16:32 28s block_mul
block_mul
November 26, 2023 16:32 28s
Added the done flags to blocks Verilog CI #14: Commit 3537a00 pushed by kir486680
November 25, 2023 16:58 30s block_mul
block_mul
November 25, 2023 16:58 30s
Adding FSM for mult. Very messy rn Verilog CI #13: Commit 10bfd83 pushed by kir486680
November 22, 2023 22:09 31s block_mul
block_mul
November 22, 2023 22:09 31s
Checking block_get dim Verilog CI #12: Commit d58ba7f pushed by kir486680
November 22, 2023 00:06 34s block_mul
block_mul
November 22, 2023 00:06 34s
added requirements.txt Verilog CI #11: Commit 50262e8 pushed by kir486680
November 21, 2023 23:29 36s block_mul
block_mul
November 21, 2023 23:29 36s
Frogot to add some files lol Verilog CI #10: Commit 8f4e27c pushed by kir486680
November 21, 2023 23:26 29s block_mul
block_mul
November 21, 2023 23:26 29s
Minor Dim Fix Verilog CI #9: Commit ced2644 pushed by kir486680
November 21, 2023 15:04 27s block_mul
block_mul
November 21, 2023 15:04 27s
Created Block Adder Verilog CI #8: Commit 0b8bdf6 pushed by kir486680
November 21, 2023 15:01 38s block_mul
block_mul
November 21, 2023 15:01 38s
Added Block Partitioning Verilog CI #7: Commit 54f4dc0 pushed by kir486680
November 21, 2023 02:29 28s block_mul
block_mul
November 21, 2023 02:29 28s
Added state Machine Verilog CI #6: Commit f6763af pushed by kir486680
November 19, 2023 17:29 30s block_mul
block_mul
November 19, 2023 17:29 30s