-
Notifications
You must be signed in to change notification settings - Fork 0
/
MCS6502.c
1444 lines (1317 loc) · 50 KB
/
MCS6502.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
//
// MCS6502.c
//
// Copyright (c) 2019 by Ben Zotto
//
// Usage is subject to the MIT License, and copyright credit must be noted
// in the documenation of binary redistributions. See accompanying LICENSE.TXT.
//
#include <string.h>
#include "MCS6502.h"
// If you uncomment the below and rebuild, you'll get a stream of
// disassembly, register and stack state printed to stdout:
//#define PRINT_DEBUG_OUTPUT
//
// 6502 Instruction Set
//
typedef enum _MCS6502AddressingMode {
MCS6502AddressingImplied, // no operand
MCS6502AddressingAccumulator, // operand is accumulator (implied)
MCS6502AddressingImmediate, // operand is single byte actual value
MCS6502AddressingZeroPage, // operand is a zero page address (high byte of addr is 0x00)
MCS6502AddressingZeroPageX, // operand is a zpg address, effective address is addr incremented by X (no carry)
MCS6502AddressingZeroPageY, // operand is a zpg address, effective address is addr incremented by Y (no carry)
MCS6502AddressingAbsolute, // operand is a complete (16-bit) address
MCS6502AddressingAbsoluteX, // operand is address, effective addr is addr incremented by X (with carry)
MCS6502AddressingAbsoluteY, // operand is address, effective addr is addr incremented by Y (with carry)
MCS6502AddressingIndirect, // operand is addrees, effective addr is the *contents* of addr. (ie, operand is a pointer)
MCS6502AddressingXIndirect, // operand is zpg address, effective addr is the 16bit word in (addr+X, addr+X+1) (no carry)
MCS6502AddressingIndirectY, // operand is zpg address, effective addr is the 16bit word in (addr, addr+1) + Y (w carry)
MCS6502AddressingRelative // operand (branch target) is PC + signed offset
} MCS6502AddressingMode;
typedef struct _MCS6502Instruction {
uint8 opcode;
char mnemonic[4];
MCS6502AddressingMode mode;
int timing;
bool timingAddOne;
} MCS6502Instruction;
MCS6502Instruction MCS6502Instructions[] = {
{ 0x69, "ADC", MCS6502AddressingImmediate, 2, false },
{ 0x65, "ADC", MCS6502AddressingZeroPage, 3, false },
{ 0x75, "ADC", MCS6502AddressingZeroPageX, 4, false },
{ 0x6D, "ADC", MCS6502AddressingAbsolute, 4, false },
{ 0x7D, "ADC", MCS6502AddressingAbsoluteX, 4, true },
{ 0x79, "ADC", MCS6502AddressingAbsoluteY, 4, true },
{ 0x61, "ADC", MCS6502AddressingXIndirect, 6, false },
{ 0x71, "ADC", MCS6502AddressingIndirectY, 5, true },
{ 0x29, "AND", MCS6502AddressingImmediate, 2, false },
{ 0x25, "AND", MCS6502AddressingZeroPage, 3, false },
{ 0x35, "AND", MCS6502AddressingZeroPageX, 4, false },
{ 0x2D, "AND", MCS6502AddressingAbsolute, 4, false },
{ 0x3D, "AND", MCS6502AddressingAbsoluteX, 4, true },
{ 0x39, "AND", MCS6502AddressingAbsoluteY, 4, true },
{ 0x21, "AND", MCS6502AddressingXIndirect, 6, false },
{ 0x31, "AND", MCS6502AddressingIndirectY, 5, true },
{ 0x0A, "ASL", MCS6502AddressingAccumulator, 2, false },
{ 0x06, "ASL", MCS6502AddressingZeroPage, 5, false },
{ 0x16, "ASL", MCS6502AddressingZeroPageX, 6, false },
{ 0x0E, "ASL", MCS6502AddressingAbsolute, 6, false },
{ 0x1E, "ASL", MCS6502AddressingAbsoluteX, 7, false },
{ 0x90, "BCC", MCS6502AddressingRelative, 0, true },
{ 0xB0, "BCS", MCS6502AddressingRelative, 0, true },
{ 0xF0, "BEQ", MCS6502AddressingRelative, 0, true },
{ 0x24, "BIT", MCS6502AddressingZeroPage, 3, false },
{ 0x2C, "BIT", MCS6502AddressingAbsolute, 4, false },
{ 0x30, "BMI", MCS6502AddressingRelative, 0, true },
{ 0xD0, "BNE", MCS6502AddressingRelative, 0, true },
{ 0x10, "BPL", MCS6502AddressingRelative, 0, true },
{ 0x00, "BRK", MCS6502AddressingImplied, 7, false },
{ 0x50, "BVC", MCS6502AddressingRelative, 0, true },
{ 0x70, "BVS", MCS6502AddressingRelative, 0, true },
{ 0x18, "CLC", MCS6502AddressingImplied, 2, false },
{ 0xD8, "CLD", MCS6502AddressingImplied, 2, false },
{ 0x58, "CLI", MCS6502AddressingImplied, 2, false },
{ 0xB8, "CLV", MCS6502AddressingImplied, 2, false },
{ 0xC9, "CMP", MCS6502AddressingImmediate, 2, false },
{ 0xC5, "CMP", MCS6502AddressingZeroPage, 3, false },
{ 0xD5, "CMP", MCS6502AddressingZeroPageX, 4, false },
{ 0xCD, "CMP", MCS6502AddressingAbsolute, 4, false },
{ 0xDD, "CMP", MCS6502AddressingAbsoluteX, 4, true },
{ 0xD9, "CMP", MCS6502AddressingAbsoluteY, 4, true },
{ 0xC1, "CMP", MCS6502AddressingXIndirect, 6, false },
{ 0xD1, "CMP", MCS6502AddressingIndirectY, 5, true },
{ 0xE0, "CPX", MCS6502AddressingImmediate, 2, false },
{ 0xE4, "CPX", MCS6502AddressingZeroPage, 3, false },
{ 0xEC, "CPX", MCS6502AddressingAbsolute, 4, false },
{ 0xC0, "CPY", MCS6502AddressingImmediate, 3, false },
{ 0xC4, "CPY", MCS6502AddressingZeroPage, 3, false },
{ 0xCC, "CPY", MCS6502AddressingAbsolute, 4, false },
{ 0xC6, "DEC", MCS6502AddressingZeroPage, 5, false },
{ 0xD6, "DEC", MCS6502AddressingZeroPageX, 6, false },
{ 0xCE, "DEC", MCS6502AddressingAbsolute, 6, false },
{ 0xDE, "DEC", MCS6502AddressingAbsoluteX, 7, false },
{ 0xCA, "DEX", MCS6502AddressingImplied, 2, false },
{ 0x88, "DEY", MCS6502AddressingImplied, 2, false },
{ 0x49, "EOR", MCS6502AddressingImmediate, 2, false },
{ 0x45, "EOR", MCS6502AddressingZeroPage, 3, false },
{ 0x55, "EOR", MCS6502AddressingZeroPageX, 4, false },
{ 0x4D, "EOR", MCS6502AddressingAbsolute, 4, false },
{ 0x5D, "EOR", MCS6502AddressingAbsoluteX, 4, true },
{ 0x59, "EOR", MCS6502AddressingAbsoluteY, 4, true },
{ 0x41, "EOR", MCS6502AddressingXIndirect, 6, false },
{ 0x51, "EOR", MCS6502AddressingIndirectY, 5, true },
{ 0xE6, "INC", MCS6502AddressingZeroPage, 5, false },
{ 0xF6, "INC", MCS6502AddressingZeroPageX, 6, false },
{ 0xEE, "INC", MCS6502AddressingAbsolute, 6, false },
{ 0xFE, "INC", MCS6502AddressingAbsoluteX, 7, false },
{ 0xE8, "INX", MCS6502AddressingImplied, 2, false },
{ 0xC8, "INY", MCS6502AddressingImplied, 2, false },
{ 0x4C, "JMP", MCS6502AddressingAbsolute, 3, false },
{ 0x6C, "JMP", MCS6502AddressingIndirect, 5, false },
{ 0x20, "JSR", MCS6502AddressingAbsolute, 6, false },
{ 0xA9, "LDA", MCS6502AddressingImmediate, 2, false },
{ 0xA5, "LDA", MCS6502AddressingZeroPage, 3, false },
{ 0xB5, "LDA", MCS6502AddressingZeroPageX, 4, false },
{ 0xAD, "LDA", MCS6502AddressingAbsolute, 4, false },
{ 0xBD, "LDA", MCS6502AddressingAbsoluteX, 4, true },
{ 0xB9, "LDA", MCS6502AddressingAbsoluteY, 4, true },
{ 0xA1, "LDA", MCS6502AddressingXIndirect, 6, false },
{ 0xB1, "LDA", MCS6502AddressingIndirectY, 5, true },
{ 0xA2, "LDX", MCS6502AddressingImmediate, 2, false },
{ 0xA6, "LDX", MCS6502AddressingZeroPage, 3, false },
{ 0xB6, "LDX", MCS6502AddressingZeroPageY, 4, false },
{ 0xAE, "LDX", MCS6502AddressingAbsolute, 4, false },
{ 0xBE, "LDX", MCS6502AddressingAbsoluteY, 4, true },
{ 0xA0, "LDY", MCS6502AddressingImmediate, 2, false },
{ 0xA4, "LDY", MCS6502AddressingZeroPage, 3, false },
{ 0xB4, "LDY", MCS6502AddressingZeroPageX, 4, false },
{ 0xAC, "LDY", MCS6502AddressingAbsolute, 4, false },
{ 0xBC, "LDY", MCS6502AddressingAbsoluteX, 4, true },
{ 0x4A, "LSR", MCS6502AddressingAccumulator, 2, false },
{ 0x46, "LSR", MCS6502AddressingZeroPage, 5, false },
{ 0x56, "LSR", MCS6502AddressingZeroPageX, 6, false },
{ 0x4E, "LSR", MCS6502AddressingAbsolute, 6, false },
{ 0x5E, "LSR", MCS6502AddressingAbsoluteX, 7, false },
{ 0xEA, "NOP", MCS6502AddressingImplied, 2, false },
{ 0x09, "ORA", MCS6502AddressingImmediate, 2, false },
{ 0x05, "ORA", MCS6502AddressingZeroPage, 3, false },
{ 0x15, "ORA", MCS6502AddressingZeroPageX, 4, false },
{ 0x0D, "ORA", MCS6502AddressingAbsolute, 4, false },
{ 0x1D, "ORA", MCS6502AddressingAbsoluteX, 4, true },
{ 0x19, "ORA", MCS6502AddressingAbsoluteY, 4, true },
{ 0x01, "ORA", MCS6502AddressingXIndirect, 6, false },
{ 0x11, "ORA", MCS6502AddressingIndirectY, 5, true },
{ 0x48, "PHA", MCS6502AddressingImplied, 3, false },
{ 0x08, "PHP", MCS6502AddressingImplied, 3, false },
{ 0x68, "PLA", MCS6502AddressingImplied, 4, false },
{ 0x28, "PLP", MCS6502AddressingImplied, 4, false },
{ 0x2A, "ROL", MCS6502AddressingAccumulator, 2, false },
{ 0x26, "ROL", MCS6502AddressingZeroPage, 5, false },
{ 0x36, "ROL", MCS6502AddressingZeroPageX, 6, false },
{ 0x2E, "ROL", MCS6502AddressingAbsolute, 6, false },
{ 0x3E, "ROL", MCS6502AddressingAbsoluteX, 7, false },
{ 0x6A, "ROR", MCS6502AddressingAccumulator, 2, false },
{ 0x66, "ROR", MCS6502AddressingZeroPage, 5, false },
{ 0x76, "ROR", MCS6502AddressingZeroPageX, 6, false },
{ 0x6E, "ROR", MCS6502AddressingAbsolute, 6, false },
{ 0x7E, "ROR", MCS6502AddressingAbsoluteX, 7, false },
{ 0x40, "RTI", MCS6502AddressingImplied, 6, false },
{ 0x60, "RTS", MCS6502AddressingImplied, 6, false },
{ 0xE9, "SBC", MCS6502AddressingImmediate, 2, false },
{ 0xE5, "SBC", MCS6502AddressingZeroPage, 3, false },
{ 0xF5, "SBC", MCS6502AddressingZeroPageX, 4, false },
{ 0xED, "SBC", MCS6502AddressingAbsolute, 4, false },
{ 0xFD, "SBC", MCS6502AddressingAbsoluteX, 4, true },
{ 0xF9, "SBC", MCS6502AddressingAbsoluteY, 4, true },
{ 0xE1, "SBC", MCS6502AddressingXIndirect, 6, false },
{ 0xF1, "SBC", MCS6502AddressingIndirectY, 5, true },
{ 0x38, "SEC", MCS6502AddressingImplied, 2, false },
{ 0xF8, "SED", MCS6502AddressingImplied, 2, false },
{ 0x78, "SEI", MCS6502AddressingImplied, 2, false },
{ 0x85, "STA", MCS6502AddressingZeroPage, 3, false },
{ 0x95, "STA", MCS6502AddressingZeroPageX, 4, false },
{ 0x8D, "STA", MCS6502AddressingAbsolute, 4, false },
{ 0x9D, "STA", MCS6502AddressingAbsoluteX, 5, false },
{ 0x99, "STA", MCS6502AddressingAbsoluteY, 5, false },
{ 0x81, "STA", MCS6502AddressingXIndirect, 6, false },
{ 0x91, "STA", MCS6502AddressingIndirectY, 6, false },
{ 0x86, "STX", MCS6502AddressingZeroPage, 3, false },
{ 0x96, "STX", MCS6502AddressingZeroPageY, 4, false },
{ 0x8E, "STX", MCS6502AddressingAbsolute, 4, false },
{ 0x84, "STY", MCS6502AddressingZeroPage, 3, false },
{ 0x94, "STY", MCS6502AddressingZeroPageX, 4, false },
{ 0x8C, "STY", MCS6502AddressingAbsolute, 4, false },
{ 0xAA, "TAX", MCS6502AddressingImplied, 2, false },
{ 0xA8, "TAY", MCS6502AddressingImplied, 2, false },
{ 0xBA, "TSX", MCS6502AddressingImplied, 2, false },
{ 0x8A, "TXA", MCS6502AddressingImplied, 2, false },
{ 0x9A, "TXS", MCS6502AddressingImplied, 2, false },
{ 0x98, "TYA", MCS6502AddressingImplied, 2, false }
};
// The above instructions are inserted into this indexed jump table the
// first time someone calls init, below.
static MCS6502Instruction *MCS6502OpcodeTable[256];
//
// Forward declarations of local private routines.
//
static inline uint8 MCS6502ReadByte(uint16 addr, MCS6502ExecutionContext * ctx);
static inline void MCS6502WriteByte(uint16 addr, uint8 byte, MCS6502ExecutionContext * ctx);
static inline void PushByte(uint8 byte, MCS6502ExecutionContext * context);
static inline void PushFlags(bool b, MCS6502ExecutionContext * context);
static inline uint8 PullByte(MCS6502ExecutionContext * context);
static inline uint16 ReadWordAtAddress(uint16 addr, MCS6502ExecutionContext * context);
static inline uint8 BCDFromInteger(int integer);
static inline int IntegerFromBCD(uint8 bcd);
static void HandleIRQ(MCS6502ExecutionContext * context);
static void HandleNMI(MCS6502ExecutionContext * context);
static uint16 EffectiveOperandAddressForInstruction(MCS6502Instruction * instruction, MCS6502ExecutionContext * context, bool * crossesPageBoundary);
static uint8 ReadOperandValueForCurrentInstruction(MCS6502Instruction * instruction, MCS6502ExecutionContext * context);
static void WriteResultForCurrentInstruction(uint8 result, MCS6502Instruction * instruction, MCS6502ExecutionContext * context);
static int LengthForInstruction(MCS6502Instruction * instruction);
static void ExecuteConditionalBranch(bool condition, MCS6502Instruction * instruction, MCS6502ExecutionContext * context);
//
// Status flag helpers.
//
#define CTXP_SET(f) (context->p |= (f))
#define CTXP_CLEAR(f) (context->p &= (~(f)))
#define CTXP_ISSET(f) ((context->p & (f)) != 0)
static inline void SetCarry(MCS6502ExecutionContext * context) { CTXP_SET(MCS6502_STATUS_C); }
static inline void ClearCarry(MCS6502ExecutionContext * context) { CTXP_CLEAR(MCS6502_STATUS_C); }
static inline bool IsCarrySet(MCS6502ExecutionContext * context) { return CTXP_ISSET(MCS6502_STATUS_C); }
static inline void SetOrClearCarry(bool c, MCS6502ExecutionContext * context) { if (c) { SetCarry(context); } else { ClearCarry(context); } }
static inline void SetZero(MCS6502ExecutionContext * context) { CTXP_SET(MCS6502_STATUS_Z); }
static inline void ClearZero(MCS6502ExecutionContext * context) { CTXP_CLEAR(MCS6502_STATUS_Z); }
static inline bool IsZeroSet(MCS6502ExecutionContext * context) { return CTXP_ISSET(MCS6502_STATUS_Z); }
static inline void UpdateZero(uint8 val, MCS6502ExecutionContext * context) { if (val == 0) { SetZero(context); } else { ClearZero(context); } }
static inline void SetInterruptDisable(MCS6502ExecutionContext * context) { CTXP_SET(MCS6502_STATUS_I); }
static inline void ClearInterruptDisable(MCS6502ExecutionContext * context) { CTXP_CLEAR(MCS6502_STATUS_I); }
static inline bool IsInterruptDisableSet(MCS6502ExecutionContext * context) { return CTXP_ISSET(MCS6502_STATUS_I); }
static inline void SetDecimal(MCS6502ExecutionContext * context) { CTXP_SET(MCS6502_STATUS_D); }
static inline void ClearDecimal(MCS6502ExecutionContext * context) { CTXP_CLEAR(MCS6502_STATUS_D); }
static inline bool IsDecimalSet(MCS6502ExecutionContext * context) { return CTXP_ISSET(MCS6502_STATUS_D); }
static inline void SetNegative(MCS6502ExecutionContext * context) { CTXP_SET(MCS6502_STATUS_N); }
static inline void ClearNegative(MCS6502ExecutionContext * context) { CTXP_CLEAR(MCS6502_STATUS_N); }
static inline bool IsNegativeSet(MCS6502ExecutionContext * context) { return CTXP_ISSET(MCS6502_STATUS_N); }
static inline void UpdateNegative(uint8 val, MCS6502ExecutionContext * context) { if ((val & 0x80) != 0) { SetNegative(context); } else { ClearNegative(context); } }
static inline void SetOverflow(MCS6502ExecutionContext * context) { CTXP_SET(MCS6502_STATUS_V); }
static inline void ClearOverflow(MCS6502ExecutionContext * context) { CTXP_CLEAR(MCS6502_STATUS_V); }
static inline bool IsOverflowSet(MCS6502ExecutionContext * context) { return CTXP_ISSET(MCS6502_STATUS_V); }
static inline void SetOrClearOverflow(bool v, MCS6502ExecutionContext * context) { if (v) { SetOverflow(context); } else { ClearOverflow(context); } }
static inline void UpdateZeroNegative(uint8 val, MCS6502ExecutionContext * context) { UpdateZero(val, context); UpdateNegative(val, context); }
#undef CTXP_SET
#undef CTXP_CLEAR
#undef CTXP_ISSET
// Debug helper:
char * DisassembleCurrentInstruction(MCS6502Instruction * instruction, MCS6502ExecutionContext * context);
//
// Public functions
//
void
MCS6502Init(
MCS6502ExecutionContext * context,
MCS6502DataReadByteFunction readByteFn,
MCS6502DataWriteByteFunction writeByteFn,
void * readWriteContext
)
{
// Blank out the context state.
memset(context, 0, sizeof(MCS6502ExecutionContext));
// Setup the data access functions.
context->readByte = readByteFn;
context->writeByte = writeByteFn;
context->readWriteContext = readWriteContext;
// Set up our static sorted opcode jump table. Zero out the table first so that
// all unoccupied slots (invalid opcodes) will be NULL.
static bool opcodesReady = false;
if (!opcodesReady) {
memset(&MCS6502OpcodeTable[0], 0, sizeof(MCS6502OpcodeTable));
int instructionCount = sizeof(MCS6502Instructions)/sizeof(MCS6502Instructions[0]);
for (int i = 0; i < instructionCount; i++) {
MCS6502Instruction * instruction = &MCS6502Instructions[i];
MCS6502OpcodeTable[instruction->opcode] = instruction;
}
opcodesReady = true;
}
}
void
MCS6502Reset(
MCS6502ExecutionContext * context
)
{
context->a = 0;
context->x = 0;
context->y = 0;
context->p = MCS6502_STATUS_I; // 6502 starts with interrupts disabled.
// Stack pointer starts at top of page 1, but lands at 0xFD (rather than 0xFF)
// after the hardware startup is complete.
context->sp = 0xFD;
// Jump to the address given at the reset vector location.
context->pc = ReadWordAtAddress(MCS6502_RESET, context);
}
void
MCS6502IRQ(
MCS6502ExecutionContext * context
)
{
if (IsInterruptDisableSet(context)) {
return;
}
if (context->pendingTiming > 0) {
context->irqPending = true;
return;
}
HandleIRQ(context);
context->pendingTiming = context->timingForLastOperation;
}
void
MCS6502NMI(
MCS6502ExecutionContext * context
)
{
if (context->pendingTiming > 0) {
context->nmiPending = true;
return;
}
HandleNMI(context);
context->pendingTiming = context->timingForLastOperation;
}
MCS6502ExecResult
MCS6502Tick(
MCS6502ExecutionContext * context
)
{
// If there are ticks pending to run down, decrement and leave.
if (context->pendingTiming > 0) {
context->pendingTiming--;
return MCS6502ExecResultRunning;
}
// If nothing is pending, execute the next instruction.
MCS6502ExecResult result = MCS6502ExecNext(context);
// Assign the operation's cycle count to the pending count, then
// decrement it to represent one tick.
context->pendingTiming = context->timingForLastOperation;
context->pendingTiming--;
return result;
}
MCS6502ExecResult
MCS6502ExecNext(
MCS6502ExecutionContext * context
)
{
// We expect to be called either by the tick function when there is nothing
// pending, or by an external caller directly who intends to immediately
// perform the next instruction. Zero out the tick counts in case
// we are looking at the latter situation, because it doesn't matter.
context->pendingTiming = 0;
// Zero out the timing for this coming operation. We may increment it in multiple
// places depending on the addressing.
context->timingForLastOperation = 0;
// If an interrupt is scheduled, do that instead of proceeding with
// standard fetch. NMI takes precedence.
if (context->nmiPending) {
HandleNMI(context);
return MCS6502ExecResultRunning;
}
if (context->irqPending) {
HandleIRQ(context);
return MCS6502ExecResultRunning;
}
// Fetch opcode
uint8 opcode = MCS6502ReadByte(context->pc, context);
MCS6502Instruction * instruction = MCS6502OpcodeTable[opcode];
if (!instruction) {
return MCS6502ExecResultInvalidOperation;
}
#ifdef PRINT_DEBUG_OUTPUT
char * dis = DisassembleCurrentInstruction(instruction, context);
fprintf(stderr, "%04X: %s\n", context->pc, dis);
#endif
// All instructions will update the PC based on the length of the instruction,
// except instructions that modify the PC directly. Flag those situations so
// we can suppress the default behavior later.
bool doNotUpdatePC = false;
// Track the original PC value so that we can known whether we are infinite-looping
// on the same address (ie, a halt). An interrupt of some kind will kick the CPU
// out of that state, but it's useful to be able to flag it.
uint16 originalPC = context->pc;
// Decode and execute op
switch (opcode) {
// ADC
case 0x69:
case 0x65:
case 0x75:
case 0x6D:
case 0x7D:
case 0x79:
case 0x61:
case 0x71:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
if (!IsDecimalSet(context)) {
unsigned int sum = context->a + operand + (IsCarrySet(context) ? 1 : 0);
// Overflow flag is set if the twos complement (signed) result is > +127 or < -128.
// The simplest way for us to do this is just do the addition as signed values and check.
int vres = (signed char)context->a + (signed char)operand + (IsCarrySet(context) ? 1 : 0);
context->a = sum & 0xFF;
SetOrClearCarry((sum > 0xFF), context);
UpdateZeroNegative(context->a, context);
SetOrClearOverflow((vres > 127 || vres < -128), context);
} else {
int operandInteger = IntegerFromBCD(operand);
int accInteger = IntegerFromBCD(context->a);
int sum = operandInteger + accInteger + (IsCarrySet(context) ? 1 : 0);
if (sum > 99) {
SetCarry(context);
sum -= 100;
} else {
ClearCarry(context);
}
context->a = BCDFromInteger(sum);
UpdateZeroNegative(context->a, context);
// Don't do anything to overflow flag. It's not documented behavior.
}
break;
}
// AND
case 0x29:
case 0x25:
case 0x35:
case 0x2D:
case 0x3D:
case 0x39:
case 0x21:
case 0x31:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
context->a = context->a & operand;
UpdateZeroNegative(context->a, context);
break;
}
// ASL
case 0x0A:
case 0x06:
case 0x16:
case 0x0E:
case 0x1E:
{
uint8 val = ReadOperandValueForCurrentInstruction(instruction, context);
SetOrClearCarry((val & 0x80) != 0, context);
val <<= 1;
UpdateZeroNegative(val, context);
WriteResultForCurrentInstruction(val, instruction, context);
break;
}
// BCC
case 0x90:
{
ExecuteConditionalBranch(!IsCarrySet(context), instruction, context);
doNotUpdatePC = true;
break;
}
// BCS
case 0xB0:
{
ExecuteConditionalBranch(IsCarrySet(context), instruction, context);
doNotUpdatePC = true;
break;
}
// BEQ
case 0xF0:
{
ExecuteConditionalBranch(IsZeroSet(context), instruction, context);
doNotUpdatePC = true;
break;
}
// BIT
case 0x24:
case 0x2C:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
uint8 and = context->a & operand;
UpdateNegative(operand, context);
UpdateZero(and, context);
SetOrClearOverflow((operand & 0x40) > 0, context);
break;
}
// BMI
case 0x30:
{
ExecuteConditionalBranch(IsNegativeSet(context), instruction, context);
doNotUpdatePC = true;
break;
}
// BNE
case 0xD0:
{
ExecuteConditionalBranch(!IsZeroSet(context), instruction, context);
doNotUpdatePC = true;
break;
}
// BPL
case 0x10:
{
ExecuteConditionalBranch(!IsNegativeSet(context), instruction, context);
doNotUpdatePC = true;
break;
}
// BRK
case 0x00:
{
uint16 nextPC = context->pc + 2; // BRK can replace a 2-byte instruction; RTI returns to actual PC.
PushByte((nextPC >> 8) & 0xFF, context);
PushByte(nextPC & 0xFF, context);
PushFlags(true, context);
SetInterruptDisable(context);
context->pc = ReadWordAtAddress(MCS6502_IRQ_BRK, context);
doNotUpdatePC = true;
break;
}
// BVC
case 0x50:
{
ExecuteConditionalBranch(!IsOverflowSet(context), instruction, context);
doNotUpdatePC = true;
break;
}
// BVS
case 0x70:
{
ExecuteConditionalBranch(IsOverflowSet(context), instruction, context);
doNotUpdatePC = true;
break;
}
// CLC
case 0x18:
{
ClearCarry(context);
break;
}
// CLD
case 0xD8:
{
ClearDecimal(context);
break;
}
// CLI
case 0x58:
{
ClearInterruptDisable(context);
break;
}
// CLV
case 0xB8:
{
ClearOverflow(context);
break;
}
// CMP
case 0xC9:
case 0xC5:
case 0xD5:
case 0xCD:
case 0xDD:
case 0xD9:
case 0xC1:
case 0xD1:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
SetOrClearCarry((context->a >= operand), context);
UpdateZero((context->a - operand), context);
UpdateNegative((context->a - operand), context);
break;
}
// CPX
case 0xE0:
case 0xE4:
case 0xEC:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
SetOrClearCarry((context->x >= operand), context);
UpdateZero((context->x - operand), context);
UpdateNegative((context->x - operand), context);
break;
}
// CPY
case 0xC0:
case 0xC4:
case 0xCC:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
SetOrClearCarry((context->y >= operand), context);
UpdateZero((context->y - operand), context);
UpdateNegative((context->y - operand), context);
break;
}
// DEC
case 0xC6:
case 0xD6:
case 0xCE:
case 0xDE:
{
uint8 val = ReadOperandValueForCurrentInstruction(instruction, context);
val--;
WriteResultForCurrentInstruction(val, instruction, context);
UpdateZeroNegative(val, context);
break;
}
// DEX
case 0xCA:
{
context->x = context->x - 1;
UpdateZeroNegative(context->x, context);
break;
}
// DEY
case 0x88:
{
context->y = context->y - 1;
UpdateZeroNegative(context->y, context);
break;
}
// EOR
case 0x49:
case 0x45:
case 0x55:
case 0x4D:
case 0x5D:
case 0x59:
case 0x41:
case 0x51:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
context->a = context->a ^ operand;
UpdateZeroNegative(context->a, context);
break;
}
// INC
case 0xE6:
case 0xF6:
case 0xEE:
case 0xFE:
{
uint8 value = ReadOperandValueForCurrentInstruction(instruction, context);
value++;
WriteResultForCurrentInstruction(value, instruction, context);
UpdateZeroNegative(value, context);
break;
}
// INX
case 0xE8:
{
context->x = context->x + 1;
UpdateZeroNegative(context->x, context);
break;
}
// INY
case 0xC8:
{
context->y = context->y + 1;
UpdateZeroNegative(context->y, context);
break;
}
// JMP
case 0x4C:
case 0x6C:
{
context->pc = EffectiveOperandAddressForInstruction(instruction, context, NULL);
doNotUpdatePC = true;
break;
}
// JSR
case 0x20:
{
uint16 destAddr = EffectiveOperandAddressForInstruction(instruction, context, NULL);
uint16 returnAddr = context->pc + 2;
// Push address of last byte of the JSR instruction, high byte first.
// RTS will always come back to address+1, hence the off by one push.
PushByte(((returnAddr >> 8) & 0xFF), context);
PushByte((returnAddr & 0xFF), context);
context->pc = destAddr;
doNotUpdatePC = true;
break;
}
// LDA
case 0xA9:
case 0xA5:
case 0xB5:
case 0xAD:
case 0xBD:
case 0xB9:
case 0xA1:
case 0xB1:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
context->a = operand;
UpdateZeroNegative(operand, context);
break;
}
// LDX
case 0xA2:
case 0xA6:
case 0xB6:
case 0xAE:
case 0xBE:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
context->x = operand;
UpdateZeroNegative(context->x, context);
break;
}
// LDY
case 0xA0:
case 0xA4:
case 0xB4:
case 0xAC:
case 0xBC:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
context->y = operand;
UpdateZeroNegative(context->y, context);
break;
}
// LSR
case 0x4A:
case 0x46:
case 0x56:
case 0x4E:
case 0x5E:
{
uint8 val = ReadOperandValueForCurrentInstruction(instruction, context);
SetOrClearCarry((val & 0x01) != 0, context);
val >>= 1;
val &= 0x7F;
UpdateZero(val, context);
ClearNegative(context);
WriteResultForCurrentInstruction(val, instruction, context);
break;
}
// NOP
case 0xEA:
{
// NOTHING
break;
}
// ORA
case 0x09:
case 0x05:
case 0x15:
case 0x0D:
case 0x1D:
case 0x19:
case 0x01:
case 0x11:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
context->a = context->a | operand;
UpdateZeroNegative(context->a, context);
break;
}
// PHA
case 0x48:
{
PushByte(context->a, context);
break;
}
// PHP
case 0x08:
{
PushFlags(true, context);
break;
}
// PLA
case 0x68:
{
context->a = PullByte(context);
UpdateZeroNegative(context->a, context);
break;
}
// PLP
case 0x28:
{
uint8 p = PullByte(context);
p &= ~(0x20 | MCS6502_STATUS_B);
context->p = p;
break;
}
// ROL
case 0x2A:
case 0x26:
case 0x36:
case 0x2E:
case 0x3E:
{
uint8 val = ReadOperandValueForCurrentInstruction(instruction, context);
bool initialCarry = IsCarrySet(context);
SetOrClearCarry((val & 0x80) > 0, context);
val <<= 1;
val &= 0xFE;
val |= (initialCarry ? 0x1 : 0x0);
WriteResultForCurrentInstruction(val, instruction, context);
UpdateZeroNegative(val, context);
break;
}
// ROR
case 0x6A:
case 0x66:
case 0x76:
case 0x6E:
case 0x7E:
{
uint8 val = ReadOperandValueForCurrentInstruction(instruction, context);
int initialCarry = IsCarrySet(context);
SetOrClearCarry((val & 0x01) > 0, context);
val >>= 1;
val &= 0x7F;
val |= (initialCarry ? 0x80 : 0);
WriteResultForCurrentInstruction(val, instruction, context);
UpdateZeroNegative(val, context);
break;
}
// RTI
case 0x40:
{
uint8 p = PullByte(context);
p &= ~(0x20 | MCS6502_STATUS_B);
context->p = p;
uint8 lo = PullByte(context);
uint8 hi = PullByte(context);
context->pc = ((hi << 8) | lo);
doNotUpdatePC = true;
break;
}
// RTS
case 0x60:
{
uint8 lo = PullByte(context);
uint8 hi = PullByte(context);
context->pc = ((hi << 8) | lo) + 1;
doNotUpdatePC = true;
break;
}
// SBC
case 0xE9:
case 0xE5:
case 0xF5:
case 0xED:
case 0xFD:
case 0xF9:
case 0xE1:
case 0xF1:
{
uint8 operand = ReadOperandValueForCurrentInstruction(instruction, context);
if (!IsDecimalSet(context)) {
// SBC is apparently exactly equivalent to ADC with the operand as ones-complement inverted, so:
operand = ~operand;
//
unsigned int sum = context->a + operand + (IsCarrySet(context) ? 1 : 0);
// Overflow flag is set if the twos complement (signed) result is > +127 or < -128.
// The simplest way for us to do this is just do the addition as signed values and check.
int vres = (signed char)context->a + (signed char)operand + (IsCarrySet(context) ? 1 : 0);
context->a = sum & 0xFF;
SetOrClearCarry(sum > 0xFF, context);
UpdateZeroNegative(context->a, context);
SetOrClearOverflow((vres > 127 || vres < -128), context);
} else {
int operandInteger = IntegerFromBCD(operand);
int accInteger = IntegerFromBCD(context->a);
int difference = accInteger - operandInteger - (IsCarrySet(context) ? 0 : 1);
if (difference < 0) {
ClearCarry(context);
difference += 100;
} else {
SetCarry(context);
}
context->a = BCDFromInteger(difference);
UpdateZeroNegative(context->a, context);
// Don't do anything to overflow flag. It's not documented behavior.
}
break;
}
// SEC
case 0x38:
{
SetCarry(context);
break;
}
// SED
case 0xF8:
{
SetDecimal(context);
break;
}
// SEI
case 0x78:
{
SetInterruptDisable(context);
break;
}
// STA
case 0x85:
case 0x95:
case 0x8D:
case 0x9D:
case 0x99:
case 0x81:
case 0x91:
{
uint16 addr = EffectiveOperandAddressForInstruction(instruction, context, NULL);
MCS6502WriteByte(addr, context->a, context);
break;
}
// STX
case 0x86:
case 0x96:
case 0x8E:
{
uint16 addr = EffectiveOperandAddressForInstruction(instruction, context, NULL);