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Up-to-date #18
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Merged
Up-to-date #18
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available for custom platform use via soc_firq_i signal
due to modified RTE / software framework
bug caused additional offset for higher baud rates
bootloader & blink_led due to fixed bug in uart configuration function
- fixed typo in note (misaligned instruction fetches are not possible WITH C-extension enabled) - removed AMOSWAP test
…egions When implementing more PMP regions that a certain critical limit an additional register stage is automatically inserted into the CPU’s memory interfaces increasing the latency of instruction fetches and data access by +1 cycle. The critical limit can be adapted for custom use by a constant from the main VHDL package file (rtl/core/neorv32_package.vhd). The default value is 4.
changed address of "unreachable memory-mapped register" to make sure this is ALWAYS unreachable
provides up to 32x32-bit of memory-mapped device registers + IRQ + custom IO
removed custom function units; added custom functions subsystem
was: 128 bytes starting at 0xFFFFFF80 is: 256 bytes starting at 0xFFFFFF00
blink_led example program -> application_image bootloader -> bootloader_image
removed custom function units 0 & 1 (CFU0 & CFU1); added new Custom Functions Subsystem (CFS)
removed custom functions units 0 & 1 (CFU0, CFU1) added new custom functions subsystem (CFS) - updated processor signals & generics - removed CFU section - added CFS section - updated CFU and CFS related configuration flags in SYSINFO module
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