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neogeo.sv
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//============================================================================
// SNK NeoGeo for MiSTer
//
// Copyright (C) 2018 Sean 'Furrtek' Gonsalves
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
// Current status:
// ADPCM kinda works, many loud glitches. DDR3 latency issue ? Signal are ready in Signaltap
// Neo CD CD check ok but crashes when loading. No more video glitches.
// How about not using a cache at all and DMAing directly from the data fed by the HPS ?
// The "sector ready" IRQ could be triggered just when a sector is requested, and the actual transfer
// could be done when the system ROM starts up the DMA transfer ?
// Neo CD times 12/05/2019:
// SECTOR_READY goes high at SECTOR_TIMER == 430631
// So it takes 600000-430631=169369 ticks to get a sector from HPS
// 169369/120M=1.41ms (1451 kB/s)
// DMA copy: 215 ticks for 10 bytes
// So 215/120M/10=179.17ns per byte (5450 kB/s)
// Neo CD times 11/05/2019:
// DMA copy: 616 ticks for 10 bytes
// So 215/120M/10=513.3ns per byte (1902 kB/s)
module emu
(
//Master input clock
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [44:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
output [7:0] VIDEO_ARX,
output [7:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
input TAPE_IN,
// SD-SPI
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
//SDRAM interface with lower latency
output SDRAM_CLK,
output SDRAM_CKE,
output [12:0] SDRAM_A,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE
);
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign AUDIO_S = 1; // Signed
assign AUDIO_MIX = status[5:4];
assign AUDIO_L = snd_left;
assign AUDIO_R = snd_right;
assign LED_USER = ioctl_download;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign VIDEO_ARX = 8'd10; // 320/32
assign VIDEO_ARY = 8'd7; // 224/32
assign VGA_DE = ~CHBL & nBNKB;
// status bit definition:
// 31 23 15 7
// --AA-PSS -------- L--CGGDD DEEMVTTR
// R: status[0] Reset, used by the HPS, keep it there
// T: status[2:1] System type, 0=Console, 1=Arcade, 2=CD, 3=CDZ
// V: status[3] Video mode
// M: status[4] Memory card presence
// E: status[6:5] Stereo mix
// D: status[9:7] DIP switches
// G: status[11:10] Neo CD region
// C: status[12] Save memory card & backup RAM
// L: status[12] CD lid state (DEBUG)
// S: status[25:24] Special chip type, 0=None, 1=PRO-CT0, 2=Link MCU, 3=NEO-CMC
// P: status[26] Use PCM chip or not
// A: status[29:28] Sprite tile # remap hack, 0=no remap, 1=kof95, 2=whp, 3=kizuna
`include "build_id.v"
// Common to all systems
localparam CONF_STR1 = {
"NEOGEO;;",
"-;"
};
localparam CONF_STR2_CART = {
"S,EP1P1,Load romset;" // F
};
localparam CONF_STR2_CD = {
"0,ISOBIN,Load ISO CD Image;" // S
};
// Common to all systems
localparam CONF_STR3 = {
"-;",
"O12,System type,Console,Arcade,CD,CDZ;",
"O3,Video mode,NTSC,PAL;",
"RC,Save memory card;"
};
localparam CONF_STR4_CART = {
"4,Memory card,Plugged,Unplugged;", // O
};
localparam CONF_STR4_CD = {
"AB,Region,US,EU,JP,AS;", // O
};
localparam CONF_STR4B_CD = {
"F,CD lid,Opened,Closed;", // O
};
localparam CONF_STR5_MVS = {
"7,DIP:Settings,OFF,ON;" // O
};
localparam CONF_STR6_MVS = {
"8,DIP:Freeplay,OFF,ON;" // O
};
localparam CONF_STR7_MVS = {
"9,DIP:Freeze,OFF,ON;", // O
};
// Common to all systems
localparam CONF_STR8 = {
"-;",
"O56,Stereo mix,none,25%,50%,100%;",
"R0,Reset & apply;",
"J1,A,B,C,D,Start,Select,Coin,ABC;", // ABC is a special key to press A+B+C at once, useful for
"V,v",`BUILD_DATE // keyboards that don't allow more than 2 keypresses at once
};
//////////////////// CLOCKS ///////////////////
wire locked;
wire clk_sys;
// 50MHz in, 5*24=120MHz out
// CAS latency = 3 (20.8ns)
pll pll(
.refclk(CLK_50M),
.rst(0),
.outclk_0(clk_sys),
.outclk_1(SDRAM_CLK), // Phase shifted
.locked(locked)
);
assign CLK_VIDEO = clk_sys;
assign CE_PIXEL = CLK_6MB;
wire nRST = ~(ioctl_download | status[0]);
// The watchdog should output nRESET but it makes video sync stop for a moment, so the
// MiSTer OSD jumps around. Provide an indication for devs that a watchdog reset happened ?
//wire nRESET = nRST;
reg nRESET;
reg nRST_PREV_24M;
reg [15:0] TRASH_ADDR;
reg TRASHING;
always @(posedge CLK_24M)
begin
nRST_PREV_24M <= nRST;
// nRST rising edge: start RAM trashing
if (~nRST_PREV_24M & nRST)
begin
TRASHING <= 1;
TRASH_ADDR <= 16'h0000;
end
// nRST falling edge: put system in reset
if (nRST_PREV_24M & ~nRST)
nRESET <= 0;
if (TRASHING)
begin
if (TRASH_ADDR == 16'hFFFF)
begin
// Trashing done: release system reset
TRASHING <= 0;
nRESET <= 1;
end
else
TRASH_ADDR <= TRASH_ADDR + 1'b1;
end
end
wire CLK_24M;
reg [2:0] counter_p = 0; // 0~4
reg diva, divb;
reg nRST_PREV;
reg [1:0] SYSTEM_TYPE;
always @(posedge clk_sys)
begin
nRST_PREV <= nRST;
if ({nRST_PREV, nRST} == 2'b01)
begin
// Rising edge of nRST
counter_p <= 3'd0;
diva <= 1'd0;
end
else
begin
if (counter_p == 3'd4)
counter_p <= 3'd0;
else
counter_p <= counter_p + 3'd1;
if (counter_p == 3'd0)
diva <= ~diva;
end
end
always @(negedge clk_sys)
begin
if ({nRST_PREV, nRST} == 2'b01)
begin
// Rising edge of nRST
SYSTEM_TYPE <= status[2:1]; // Latch the system type on reset
divb <= 1'd0;
end
else
begin
if (counter_p == 3'd3)
divb <= ~divb;
end
end
assign CLK_24M = diva ^ divb; // Glitch-less divide-by-5
////////////////// HPS I/O ///////////////////
// VD 0: CD bin file
// VD 1: CD cue file, let MiSTer binary take care of it, do not touch !
// VD 2: Save file
wire [2:0] img_mounted;
wire [2:0] sd_rd;
wire [2:0] sd_wr;
wire sd_ack, sd_buff_wr, img_readonly;
wire [7:0] sd_buff_addr; // Address inside 256-word sector
wire [15:0] sd_buff_dout;
wire [15:0] sd_buff_din;
wire [15:0] sd_req_type;
wire [63:0] img_size;
reg ioctl_download_prev;
reg memcard_load = 0;
reg memcard_ena = 0;
reg memcard_loading = 0;
reg memcard_state = 0;
reg memcard_save_prev = 0, sd_ack_prev;
reg [31:0] sd_lba;
wire [31:0] CD_sd_lba;
wire [15:0] joystick_0; // ----HNLS DCBAUDLR
wire [15:0] joystick_1;
wire [1:0] buttons;
wire forced_scandoubler;
wire [31:0] status;
wire [64:0] rtc;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [15:0] ioctl_dout;
wire ioctl_download;
wire [7:0] ioctl_index;
reg ioctl_wait = 0;
wire SYSTEM_MVS = (SYSTEM_TYPE == 2'd1);
wire SYSTEM_CDx = SYSTEM_TYPE[1];
// Conditional modification of the CONF strings chaining according to chosen system type
wire [7:0] char_cart_file = SYSTEM_CDx ? "+" : "F";
wire [7:0] char_cd_img = SYSTEM_CDx ? "S" : "+";
wire [7:0] char_cart_option = SYSTEM_CDx ? "+" : "O";
wire [7:0] char_mvs_option = SYSTEM_MVS ? "O" : "+";
wire [7:0] char_cd_option = SYSTEM_CDx ? "O" : "+";
// Con Arc CD CDz
// SYSTEM_TYPE 00 01 10 11
// char_cart_file F F + +
// char_cd_img + + S S
// char_cart_option O O + +
// char_mvs_option + O + +
// char_cd_option + + O O
hps_io #(
.STRLEN(
($size(CONF_STR1)>>3) +
($size(CONF_STR2_CART)>>3) +
($size(CONF_STR2_CD)>>3) +
($size(CONF_STR3)>>3) +
($size(CONF_STR4_CART)>>3) +
($size(CONF_STR4_CD)>>3) +
($size(CONF_STR4B_CD)>>3) +
($size(CONF_STR5_MVS)>>3) +
($size(CONF_STR6_MVS)>>3) +
($size(CONF_STR7_MVS)>>3) +
($size(CONF_STR8)>>3) + 8), .WIDE(1)) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.conf_str({
CONF_STR1,
char_cart_file, CONF_STR2_CART,
char_cd_img, CONF_STR2_CD,
CONF_STR3,
char_cart_option, CONF_STR4_CART,
char_cd_option, CONF_STR4_CD,
char_cd_option, CONF_STR4B_CD,
char_mvs_option, CONF_STR5_MVS,
char_mvs_option, CONF_STR6_MVS,
char_mvs_option, CONF_STR7_MVS,
CONF_STR8
}),
//.ps2_mouse(ps2_mouse), // Could be used for The Irritating Maze ?
.joystick_0(joystick_0), .joystick_1(joystick_1),
.buttons(buttons), // DE10 buttons ?
.status(status), // status read (32 bits)
.RTC(rtc),
// Loading signals
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout),
.ioctl_download(ioctl_download),
.ioctl_index(ioctl_index),
.ioctl_wait(ioctl_wait),
.sd_lba(sd_req_type ? CD_sd_lba : sd_lba),
.sd_rd(sd_rd), .sd_wr(sd_wr),
.sd_ack(sd_ack),
.sd_buff_addr(sd_buff_addr),
.sd_buff_dout(sd_buff_dout),
.sd_buff_din(sd_buff_din),
.sd_buff_wr(sd_buff_wr),
.sd_req_type(sd_req_type),
.img_mounted(img_mounted),
.img_readonly(img_readonly),
.img_size(img_size)
);
////////////////// Her Majesty ///////////////////
wire [15:0] snd_right;
wire [15:0] snd_left;
wire sdram_ready; //, ready_fourth;
wire [24:0] sdram_addr;
wire nRESETP, nSYSTEM, CARD_WE, SHADOW, nVEC, nREGEN, nSRAMWEN, PALBNK;
wire CD_nRESET_Z80;
// Clocks
wire CLK_12M, CLK_68KCLK, CLK_68KCLKB, CLK_8M, CLK_6MB, CLK_4M, CLK_4MB, CLK_1HB;
// 68k stuff
wire [15:0] M68K_DATA;
wire [23:1] M68K_ADDR;
wire A22Z, A23Z;
wire M68K_RW, nAS, nLDS, nUDS, nDTACK, nHALT, nBR, nBG, nBGACK;
wire [15:0] M68K_DATA_BYTE_MASK;
wire [15:0] FX68K_DATAIN;
wire [15:0] FX68K_DATAOUT;
wire IPL0, IPL1;
wire FC0, FC1, FC2;
reg [1:0] P_BANK;
// RTC stuff
wire RTC_DOUT, RTC_DIN, RTC_CLK, RTC_STROBE, RTC_TP;
// OEs and WEs
wire nSROMOEL, nSROMOEU, nSROMOE;
wire nROMOEL, nROMOEU;
wire nPORTOEL, nPORTOEU, nPORTWEL, nPORTWEU, nPORTADRS;
wire nSRAMOEL, nSRAMOEU, nSRAMWEL, nSRAMWEU;
wire nWRL, nWRU, nWWL, nWWU;
wire nLSPOE, nLSPWE;
wire nPAL, nPAL_WE;
wire nBITW0, nBITW1, nBITWD0, nDIPRD0, nDIPRD1;
wire nSDROE, nSDPOE;
// RAM outputs
wire [7:0] WRAML_OUT;
wire [7:0] WRAMU_OUT;
wire [15:0] SRAM_OUT;
// Memory card stuff
wire [23:0] CDA;
wire [2:0] BNK;
wire [7:0] CDD;
wire nCD1, nCD2;
wire nCRDO, nCRDW, nCRDC;
wire nCARDWEN, CARDWENB;
// Z80 stuff
wire [7:0] SDD_IN;
wire [7:0] SDD_OUT;
wire [7:0] SDD_RD_C1;
wire [15:0] SDA;
wire nSDRD, nSDWR, nMREQ, nIORQ;
wire nZ80INT, nZ80NMI, nSDW, nSDZ80R, nSDZ80W, nSDZ80CLR;
wire nSDROM, nSDMRD, nSDMWR, SDRD0, SDRD1, nZRAMCS;
wire n2610CS, n2610RD, n2610WR;
// Graphics stuff
wire [23:0] PBUS;
wire [7:0] LO_ROM_DATA;
wire nPBUS_OUT_EN;
wire [19:0] C_LATCH;
reg [3:0] C_LATCH_EXT;
wire [63:0] CR_DOUBLE;
wire [25:0] CROM_ADDR;
wire [1:0] FIX_BANK;
wire [15:0] S_LATCH;
wire [7:0] FIXD;
wire [14:0] FIXMAP_ADDR;
wire CWE, BWE, BOE;
wire [14:0] SLOW_VRAM_ADDR;
reg [15:0] SLOW_VRAM_DATA_IN;
wire [15:0] SLOW_VRAM_DATA_OUT;
wire [10:0] FAST_VRAM_ADDR;
wire [15:0] FAST_VRAM_DATA_IN;
wire [15:0] FAST_VRAM_DATA_OUT;
wire [11:0] PAL_RAM_ADDR;
wire [15:0] PAL_RAM_DATA;
reg [15:0] PAL_RAM_REG;
wire PCK1, PCK2, EVEN1, EVEN2, LOAD, H;
wire DOTA, DOTB;
wire CA4, S1H1, S2H1;
wire CHBL, nBNKB, VCS;
wire CHG, LD1, LD2, SS1, SS2;
wire [3:0] GAD;
wire [3:0] GBD;
wire [3:0] WE;
wire [3:0] CK;
wire CD_VIDEO_EN, CD_FIX_EN, CD_SPR_EN;
// SDRAM multiplexing stuff
wire [15:0] SROM_DATA;
wire [15:0] PROM_DATA;
parameter INDEX_SPROM = 0;
parameter INDEX_LOROM = 1;
parameter INDEX_SFIXROM = 2;
parameter INDEX_P1ROM_A = 4;
parameter INDEX_P1ROM_B = 5;
parameter INDEX_P2ROM = 6;
parameter INDEX_S1ROM = 8;
parameter INDEX_M1ROM = 9;
parameter INDEX_VROMS = 16;
parameter INDEX_CROMS = 64;
wire memcard_save = status[12];
wire [1:0] cart_chip = status[25:24];
wire video_mode = status[3];
wire use_pcm = status[26];
// Memory card and backup ram image save/load
always @(posedge clk_sys)
begin
ioctl_download_prev <= ioctl_download;
// Disable memcard operations on download start
if(~ioctl_download_prev & ioctl_download)
memcard_ena <= 0;
// Enable memcard operations while not downloading, 'disk' #2 is mounted, has a != 0 size, and is writable
if(~ioctl_download && img_mounted[2] && img_size && ~img_readonly)
memcard_ena <= 1;
// Start memcard image load on download end
// TODO: Trigger this on reset release, not download end ! Confuses Neo CD
if (ioctl_download_prev & ~ioctl_download)
memcard_load <= 1;
else if (memcard_state)
memcard_load <= 0;
memcard_save_prev <= memcard_save;
sd_ack_prev <= sd_ack;
if (~sd_ack_prev & sd_ack)
{sd_rd[2], sd_wr[2]} <= 2'b00;
else
begin
if (!memcard_state)
begin
// No current memcard operation
if (memcard_ena & (memcard_load | (~memcard_save_prev & memcard_save)))
begin
// Start operation
memcard_state <= 1;
memcard_loading <= memcard_load;
sd_lba <= 32'd0;
sd_rd[2] <= memcard_load;
sd_wr[2] <= ~memcard_load;
end
end
else
begin
if (sd_ack_prev & ~sd_ack)
begin
// On ack falling edge, either increase lba and continue, or stop operation
if ((SYSTEM_CDx & (sd_lba[7:0] >= 8'd15)) | // 8kB / 256 words per sector / 2 bytes per word
(~SYSTEM_CDx & (sd_lba[7:0] >= 8'd131))) // (64kB + 2kB) / 256 words per sector / 2 bytes per word
begin
memcard_loading <= 0; // Useless ?
memcard_state <= 0;
end
else
begin
sd_lba <= sd_lba + 1'd1;
sd_rd[2] <= memcard_loading;
sd_wr[2] <= ~memcard_loading;
end
end
end
end
end
wire [1:0] CD_REGION;
always @(status[11:10])
begin
// CD Region code remap:
// status[11:10] remap
// 00 10 US
// 01 01 EU
// 10 11 JP
// 11 00 ASIA
case(status[11:10])
2'b00: CD_REGION = 2'b10;
2'b01: CD_REGION = 2'b01;
2'b10: CD_REGION = 2'b11;
2'b11: CD_REGION = 2'b00;
endcase
end
wire [2:0] CD_TR_AREA; // Transfer area code
wire [15:0] CD_TR_WR_DATA;
wire [19:1] CD_TR_WR_ADDR;
wire [1:0] CD_BANK_SPR;
wire CD_TR_WR_SPR, CD_TR_WR_PCM, CD_TR_WR_Z80, CD_TR_WR_FIX;
wire CD_BANK_PCM;
wire CD_IRQ;
wire DMA_RUNNING, DMA_WR_OUT, DMA_RD_OUT;
wire [15:0] DMA_DATA_OUT;
wire [23:0] DMA_ADDR_IN;
wire [23:0] DMA_ADDR_OUT;
wire [1:0] wtbt;
cd_sys cdsystem(
.nRESET(nRESET),
.clk_sys(clk_sys), .CLK_68KCLK(CLK_68KCLK),
.M68K_ADDR(M68K_ADDR), .M68K_DATA(M68K_DATA), .A22Z(A22Z), .A23Z(A23Z),
.nLDS(nLDS), .nUDS(nUDS), .M68K_RW(M68K_RW), .nAS(nAS), .nDTACK(nDTACK),
.nBR(nBR), .nBG(nBG), .nBGACK(nBGACK),
.SYSTEM_TYPE(SYSTEM_TYPE),
.CD_REGION(CD_REGION),
.CD_LID(status[15]), // CD lid state (DEBUG)
.CD_VIDEO_EN(CD_VIDEO_EN), .CD_FIX_EN(CD_FIX_EN), .CD_SPR_EN(CD_SPR_EN),
.CD_nRESET_Z80(CD_nRESET_Z80),
.CD_TR_WR_SPR(CD_TR_WR_SPR), .CD_TR_WR_PCM(CD_TR_WR_PCM),
.CD_TR_WR_Z80(CD_TR_WR_Z80), .CD_TR_WR_FIX(CD_TR_WR_FIX),
.CD_TR_AREA(CD_TR_AREA),
.CD_BANK_SPR(CD_BANK_SPR), .CD_BANK_PCM(CD_BANK_PCM),
.CD_TR_WR_DATA(CD_TR_WR_DATA), .CD_TR_WR_ADDR(CD_TR_WR_ADDR),
.CD_IRQ(CD_IRQ), .IACK(IACK),
.sd_req_type(sd_req_type),
.sd_rd(sd_rd[0]), .sd_ack(sd_ack), .sd_buff_wr(sd_buff_wr),
.sd_buff_dout(sd_buff_dout), .sd_lba(CD_sd_lba),
.DMA_RUNNING(DMA_RUNNING),
.DMA_DATA_IN(PROM_DATA), .DMA_DATA_OUT(DMA_DATA_OUT),
.DMA_WR_OUT(DMA_WR_OUT), .DMA_RD_OUT(DMA_RD_OUT),
.DMA_ADDR_IN(DMA_ADDR_IN), // Used for reading
.DMA_ADDR_OUT(DMA_ADDR_OUT), // Used for writing
.DMA_SDRAM_BUSY(DMA_SDRAM_BUSY)
);
// The P1 zone is writable on the Neo CD
// Is there a write enable register for it ?
wire CD_EXT_WR = DMA_RUNNING ? (SYSTEM_CDx & (DMA_ADDR_OUT[23:21] == 3'd0) & DMA_WR_OUT) : // DMA writes to $000000~$1FFFFF
(SYSTEM_CDx & ~|{A23Z, A22Z, M68K_ADDR[21]} & ~M68K_RW & ~nAS); // CPU writes to $000000~$1FFFFF
wire CD_WR_SDRAM_SIG = SYSTEM_CDx & |{CD_TR_WR_SPR, CD_TR_WR_FIX, CD_EXT_WR};
wire nROMOE = nROMOEL & nROMOEU;
wire nPORTOE = nPORTOEL & nPORTOEU;
// CD system work ram is in SDRAM
wire CD_EXT_RD = DMA_RUNNING ? (SYSTEM_CDx & (DMA_ADDR_IN[23:21] == 3'd0) & DMA_RD_OUT) : // DMA reads from $000000~$1FFFFF
(SYSTEM_CDx & (~nWRL | ~nWRU)); // CPU reads from $100000~$1FFFFF
wire [63:0] sdram_dout;
wire [15:0] sdram_din;
wire sdram_rd = ioctl_download ? 1'b0 : SDRAM_RD_PULSE;
// ioctl_download is used to load the system ROM on CD systems, we need it !
wire sdram_we = SYSTEM_CDx ? (ioctl_download & (ioctl_index == INDEX_SPROM)) ? ioctl_wr : SDRAM_WR_PULSE :
(ioctl_download & (ioctl_index != INDEX_LOROM) & (ioctl_index != INDEX_M1ROM) & ((ioctl_index < INDEX_VROMS) | (ioctl_index >= INDEX_CROMS))) ? ioctl_wr : 1'b0;
wire [24:0] ioctl_addr_offset =
(ioctl_index == INDEX_SPROM) ? {6'b0_0110_0, ioctl_addr[18:0]} : // System ROM: $0600000~$067FFFF
(ioctl_index == INDEX_S1ROM) ? {6'b0_0110_1, ioctl_addr[18:0]} : // S1: $0680000~$07FFFFF
(ioctl_index == INDEX_SFIXROM) ? {8'b0_0110_001, ioctl_addr[16:0]} : // SFIX: $0620000~$063FFFF
(ioctl_index == INDEX_P1ROM_A) ? {5'b0_0000, ioctl_addr[19:0]} : // P1 first half or full: $0000000~$00FFFFF
(ioctl_index == INDEX_P1ROM_B) ? {6'b0_0000_1, ioctl_addr[18:0]} : // P1 second half: $0080000~$00FFFFF
(ioctl_index == INDEX_P2ROM) ? ioctl_addr + 25'h0200000 : // P2+: $0200000~$05FFFFF
(ioctl_index >= INDEX_CROMS) ? {ioctl_addr[23:0], 1'b0} + {ioctl_index[5:1], 18'h00000, ioctl_index[0], 1'b0} + 25'h0800000 : // C*: $0800000~$1FFFFFF
25'h0000000;
sdram_mux SDRAM_MUX(
.nRESET(nRESET),
.clk_sys(clk_sys),
.M68K_ADDR(M68K_ADDR), .M68K_DATA(M68K_DATA),
.nAS(nAS), .nLDS(nLDS), .nUDS(nUDS),
.SDRAM_DQ(SDRAM_DQ),
.CD_TR_AREA(CD_TR_AREA),
.CD_EXT_RD(CD_EXT_RD),
.CD_EXT_WR(CD_EXT_WR),
.DMA_ADDR_OUT(DMA_ADDR_OUT), .DMA_ADDR_IN(DMA_ADDR_IN),
.DMA_DATA_OUT(DMA_DATA_OUT),
.DMA_WR_OUT(DMA_WR_OUT),
.DMA_RUNNING(DMA_RUNNING),
.DMA_SDRAM_BUSY(DMA_SDRAM_BUSY),
.CD_WR_SDRAM_SIG(CD_WR_SDRAM_SIG),
.PCK1(PCK1), .PCK2(PCK2),
.CD_BANK_SPR(CD_BANK_SPR),
.P_BANK(P_BANK),
.CROM_ADDR(CROM_ADDR[24:0]),
.S_LATCH(S_LATCH),
.SDRAM_WR_PULSE(SDRAM_WR_PULSE), .SDRAM_RD_PULSE(SDRAM_RD_PULSE), .SDRAM_RD_TYPE(sdram_rd_type),
.SROM_DATA(SROM_DATA), .PROM_DATA(PROM_DATA), .CR_DOUBLE(CR_DOUBLE),
.PROM_DATA_READY(PROM_DATA_READY),
.FIX_BANK(FIX_BANK),
.SPR_EN(SPR_EN), .FIX_EN(FIX_EN),
.ioctl_download(ioctl_download),
.ioctl_addr_offset(ioctl_addr_offset),
.ioctl_dout(ioctl_dout),
.nSYSTEM_G(nSYSTEM_G), .SYSTEM_CDx(SYSTEM_CDx),
.nROMOE(nROMOE), .nPORTOE(nPORTOE), .nSROMOE(nSROMOE),
.sdram_addr(sdram_addr),
.sdram_dout(sdram_dout), .sdram_din(sdram_din),
.wtbt(wtbt),
.sdram_ready(sdram_ready) //, .ready_fourth(ready_fourth)
);
sdram ram(
.*, // Connect all nets with the same names (SDRAM_* pins)
.init(~locked), // Init SDRAM as soon as the PLL is locked
.clk(clk_sys),
.addr(sdram_addr),
.dout(sdram_dout), .din(sdram_din),
.wtbt(wtbt), // Always used in 16-bit mode except for CD fix data write
.we(sdram_we), .rd(sdram_rd), .rd_type(sdram_rd_type),
.ready(sdram_ready)
);
neo_d0 D0(
.CLK_24M(CLK_24M),
.nRESET(nRESET), .nRESETP(nRESETP),
.CLK_12M(CLK_12M), .CLK_68KCLK(CLK_68KCLK), .CLK_68KCLKB(CLK_68KCLKB), .CLK_6MB(CLK_6MB), .CLK_1HB(CLK_1HB),
.M68K_ADDR_A4(M68K_ADDR[4]),
.M68K_DATA(M68K_DATA[5:0]),
.nBITWD0(nBITWD0),
.SDA_H(SDA[15:11]), .SDA_L(SDA[4:2]),
.nSDRD(nSDRD), .nSDWR(nSDWR), .nMREQ(nMREQ), .nIORQ(nIORQ),
.nZ80NMI(nZ80NMI),
.nSDW(nSDW), .nSDZ80R(nSDZ80R), .nSDZ80W(nSDZ80W), .nSDZ80CLR(nSDZ80CLR),
.nSDROM(nSDROM), .nSDMRD(nSDMRD), .nSDMWR(nSDMWR), .nZRAMCS(nZRAMCS),
.SDRD0(SDRD0), .SDRD1(SDRD1),
.n2610CS(n2610CS), .n2610RD(n2610RD), .n2610WR(n2610WR),
.BNK(BNK)
);
// Re-priority-encode the interrupt lines with the CD_IRQ one (IPL* are active-low)
// Also swap IPL0 and IPL1 for CD systems
// Cartridge CD
// CD_IRQ IPL1 IPL0 IPL2 IPL1 IPL0 IPL2 IPL1 IPL0
// 0 1 1 1 1 1 1 1 1 No IRQ
// 0 1 0 1 1 0 1 0 1 Vblank
// 0 0 1 1 0 1 1 1 0 Timer
// 0 0 0 1 0 0 1 0 0 Cold boot
// 1 x x 1 1 1 0 1 1 CD vectored IRQ
wire IPL0_OUT = SYSTEM_CDx ? CD_IRQ | IPL1 : IPL0;
wire IPL1_OUT = SYSTEM_CDx ? CD_IRQ | IPL0 : IPL1;
wire IPL2_OUT = ~(SYSTEM_CDx & CD_IRQ);
// Because of the SDRAM latency, nDTACK is handled differently for ROM zones
// If the address is in a ROM zone, PROM_DATA_READY is used to extend the normal nDTACK output by NEO-C1
wire nDTACK_ADJ = ~&{nSROMOE, nROMOE, nPORTOE} ? ~PROM_DATA_READY | nDTACK : nDTACK;
cpu_68k M68KCPU(
.CLK_24M(CLK_24M),
.nRESET(nRESET),
.M68K_ADDR(M68K_ADDR),
.FX68K_DATAIN(FX68K_DATAIN), .FX68K_DATAOUT(FX68K_DATAOUT),
.nLDS(nLDS), .nUDS(nUDS), .nAS(nAS), .M68K_RW(M68K_RW),
.nDTACK(nDTACK_ADJ), // nDTACK
.IPL2(IPL2_OUT), .IPL1(IPL1_OUT), .IPL0(IPL0_OUT),
.FC2(FC2), .FC1(FC1), .FC0(FC0),
.nBG(nBG), .nBR(nBR), .nBGACK(nBGACK)
);
wire IACK = &{FC2, FC1, FC0};
// FX68K doesn't like byte masking with Z's, replace with 0's:
assign M68K_DATA_BYTE_MASK = (~|{nLDS, nUDS}) ? M68K_DATA :
(~nLDS) ? {8'h00, M68K_DATA[7:0]} :
(~nUDS) ? {M68K_DATA[15:8], 8'h00} :
16'h0000;
assign M68K_DATA = M68K_RW ? 16'bzzzzzzzz_zzzzzzzz : FX68K_DATAOUT;
assign FX68K_DATAIN = M68K_RW ? M68K_DATA_BYTE_MASK : 16'h0000;
assign FIXD = S2H1 ? SROM_DATA[15:8] : SROM_DATA[7:0];
// Disable ROM read in PORT zone if the game uses a special chip
assign M68K_DATA = (nROMOE & nSROMOE & |{nPORTOE, cart_chip}) ? 16'bzzzzzzzzzzzzzzzz : PROM_DATA;
// 68k work RAM
wire [14:0] WRAM_ADDR = TRASHING ? TRASH_ADDR[14:0] : M68K_ADDR[15:1];
wire [15:0] WRAM_DIN = TRASHING ? TRASH_ADDR[15:0] : M68K_DATA;
wire WRAM_WR_L = (~nWWL | TRASHING); // ~SYSTEM_CDx & TESTING
wire WRAM_WR_U = (~nWWU | TRASHING); // ~SYSTEM_CDx & TESTING
m68k_ram WRAML(WRAM_ADDR, CLK_24M, WRAM_DIN[7:0], WRAM_WR_L, WRAML_OUT);
m68k_ram WRAMU(WRAM_ADDR, CLK_24M, WRAM_DIN[15:8], WRAM_WR_U, WRAMU_OUT);
// Work RAM or CD extended RAM read
assign M68K_DATA[7:0] = nWRL ? 8'bzzzzzzzz : SYSTEM_CDx ? PROM_DATA[7:0] : WRAML_OUT;
assign M68K_DATA[15:8] = nWRU ? 8'bzzzzzzzz : SYSTEM_CDx ? PROM_DATA[15:8] : WRAMU_OUT;
// Backup RAM
wire nBWL = nSRAMWEL | nSRAMWEN_G;
wire nBWU = nSRAMWEU | nSRAMWEN_G;
wire [15:0] sd_buff_din_sram;
wire [14:0] sram_addr = {sd_lba[6:0], sd_buff_addr};
// Enable writes for save file's 000000~00FFFF
wire sram_wr = SYSTEM_MVS & ~sd_lba[7] & sd_buff_wr & sd_ack;
backup BACKUP(
.CLK_24M(CLK_24M),
.M68K_ADDR(M68K_ADDR[15:1]),
.M68K_DATA(M68K_DATA),
.nBWL(nBWL), .nBWU(nBWU),
.SRAM_OUT(SRAM_OUT),
.clk_sys(clk_sys),
.sram_addr(sram_addr),
.sram_wr(sram_wr),
.sd_buff_dout(sd_buff_dout),
.sd_buff_din_sram(sd_buff_din_sram)
);
// Backup RAM is only for MVS
assign M68K_DATA[7:0] = (nSRAMOEL | ~SYSTEM_MVS) ? 8'bzzzzzzzz : SRAM_OUT[7:0];
assign M68K_DATA[15:8] = (nSRAMOEU | ~SYSTEM_MVS) ? 8'bzzzzzzzz : SRAM_OUT[15:8];
// Memory card
assign {nCD1, nCD2} = {2{status[4] & ~SYSTEM_CDx}}; // Always plugged in CD systems
assign CARD_WE = (SYSTEM_CDx | (~nCARDWEN & CARDWENB)) & ~nCRDW;
wire [15:0] sd_buff_din_memcard;
wire [11:0] memcard_addr = {sd_lba[3:0], sd_buff_addr};
wire memcard_wr = SYSTEM_CDx ? (sd_req_type == 16'h0000) & sd_buff_wr & sd_ack : // Enable writes for save file's 000000+
sd_lba[7] & sd_buff_wr & sd_ack; // Enable writes for save file's 010000+
memcard MEMCARD(
.CLK_24M(CLK_24M),
.SYSTEM_CDx(SYSTEM_CDx),
.CDA(CDA), .CDD(CDD),
.CARD_WE(CARD_WE),
.M68K_DATA(M68K_DATA[7:0]),
.clk_sys(clk_sys),
.memcard_addr(memcard_addr),
.memcard_wr(memcard_wr),
.sd_buff_dout(sd_buff_dout),
.sd_buff_din_memcard(sd_buff_din_memcard)
);
// Feed save file writer with backup RAM data or memory card data
assign sd_buff_din = SYSTEM_CDx ? sd_buff_din_memcard :
sd_lba[7] ? sd_buff_din_memcard : sd_buff_din_sram;
// Cartridge stuff
/*gap_hack GAPHACK(
{C_LATCH_EXT, C_LATCH[19:4]},
C_LATCH[3:0],
status[29:28],
CROM_ADDR
);*/
assign CROM_ADDR = {C_LATCH_EXT[1:0] + 2'd1, C_LATCH, 3'b000};
zmc ZMC(
.nSDRD0(SDRD0),
.SDA_L(SDA[1:0]), .SDA_U(SDA[15:8]),
.MA(MA)
);
// Bankswitching for the PORT zone, do all games use a 1MB window ?
// P_BANK stays at 0 for CD systems
always @(posedge nPORTWEL or negedge nRESET)
begin
if (!nRESET)
P_BANK <= 2'd0;
else
if (!SYSTEM_CDx) P_BANK <= M68K_DATA[1:0];
end
// PRO-CT0 used as security chip
wire [3:0] GAD_SEC;
wire [3:0] GBD_SEC;
zmc2_dot ZMC2DOT(
.CLK_12M(nPORTWEL),
.EVEN(M68K_ADDR[2]), .LOAD(M68K_ADDR[1]), .H(M68K_ADDR[3]),
.CR({
M68K_ADDR[19], M68K_ADDR[15], M68K_ADDR[18], M68K_ADDR[14],
M68K_ADDR[17], M68K_ADDR[13], M68K_ADDR[16], M68K_ADDR[12],
M68K_ADDR[11], M68K_ADDR[7], M68K_ADDR[10], M68K_ADDR[6],
M68K_ADDR[9], M68K_ADDR[5], M68K_ADDR[8], M68K_ADDR[4],
M68K_DATA[15], M68K_DATA[11], M68K_DATA[14], M68K_DATA[10],
M68K_DATA[13], M68K_DATA[9], M68K_DATA[12], M68K_DATA[8],
M68K_DATA[7], M68K_DATA[3], M68K_DATA[6], M68K_DATA[2],
M68K_DATA[5], M68K_DATA[1], M68K_DATA[4], M68K_DATA[0]
}),
.GAD(GAD_SEC), .GBD(GBD_SEC)
);
assign M68K_DATA[7:0] = ((cart_chip == 2'd1) & ~nPORTOEL) ?
{GBD_SEC[1], GBD_SEC[0], GBD_SEC[3], GBD_SEC[2],
GAD_SEC[1], GAD_SEC[0], GAD_SEC[3], GAD_SEC[2]} : 8'bzzzzzzzz;
neo_273 NEO273(
.PBUS(PBUS[19:0]),
.PCK1B(~PCK1), .PCK2B(~PCK2),
.C_LATCH(C_LATCH), .S_LATCH(S_LATCH)
);
// 4 MSBs not handled by NEO-273
always @(negedge PCK1)
C_LATCH_EXT <= PBUS[23:20];
wire [1:0] CMC_FIX_BANK;
cmc_fix CMCFIX(
.PCK2B(~PCK2),
.PBUS(PBUS[15:0]),
.FIXMAP_ADDR(FIXMAP_ADDR),
.FIX_BANK(CMC_FIX_BANK)
);
// NEO-CMC handles this, set to 0 for now ()
assign FIX_BANK = (cart_chip == 2'd3) ? CMC_FIX_BANK : 2'b00;
// Fake COM MCU
wire [15:0] COM_DOUT;
com COM(
.nRESET(nRESET),
.CLK_24M(CLK_24M),
.nPORTOEL(nPORTOEL), .nPORTOEU(nPORTOEU), .nPORTWEL(nPORTWEL),
.M68K_DIN(COM_DOUT)
);
assign M68K_DATA = (cart_chip == 2'd2) ? COM_DOUT : 16'bzzzzzzzz_zzzzzzzz;
syslatch SL(
.nRESET(nRESET),
.CLK_68KCLK(CLK_68KCLK),
.M68K_ADDR(M68K_ADDR[4:1]),
.nBITW1(nBITW1),
.SHADOW(SHADOW), .nVEC(nVEC), .nCARDWEN(nCARDWEN), .CARDWENB(CARDWENB), .nREGEN(nREGEN), .nSYSTEM(nSYSTEM), .nSRAMWEN(nSRAMWEN), .PALBNK(PALBNK)
);
wire nSRAMWEN_G = SYSTEM_MVS ? nSRAMWEN : 1'b1; // nSRAMWEN is only for MVS
wire nSYSTEM_G = SYSTEM_MVS ? nSYSTEM : 1'b1; // nSYSTEM is only for MVS
neo_e0 E0(
.M68K_ADDR(M68K_ADDR[23:1]),
.BNK(BNK),
.nSROMOEU(nSROMOEU), .nSROMOEL(nSROMOEL), .nSROMOE(nSROMOE),
.nVEC(nVEC),
.A23Z(A23Z), .A22Z(A22Z),
.CDA(CDA)
);
neo_f0 F0(
.nRESET(nRESET),
.nDIPRD0(nDIPRD0), .nDIPRD1(nDIPRD1),
.nBITW0(nBITW0), .nBITWD0(nBITWD0),
.DIPSW({~status[9:8], 5'b11111, ~status[7]}),
.COIN1(~joystick_0[10]), .COIN2(~joystick_1[10]),
.M68K_ADDR(M68K_ADDR[7:4]),
.M68K_DATA(M68K_DATA[7:0]),
.SYSTEMB(~nSYSTEM_G),
.RTC_DOUT(RTC_DOUT), .RTC_TP(RTC_TP), .RTC_DIN(RTC_DIN), .RTC_CLK(RTC_CLK), .RTC_STROBE(RTC_STROBE),
.SYSTEM_TYPE(SYSTEM_MVS)
);