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  • Updated Home (markdown)

    @enjoy-digital enjoy-digital committed Jul 31, 2024
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  • Updated Tutorials Resources (markdown)

    @enjoy-digital enjoy-digital committed Jul 9, 2024
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  • Updated Tutorials Resources (markdown)

    @enjoy-digital enjoy-digital committed Jul 9, 2024
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  • Updated Tutorials Resources (markdown)

    @enjoy-digital enjoy-digital committed Jul 9, 2024
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  • Updated Tutorials Resources (markdown)

    @enjoy-digital enjoy-digital committed Jul 9, 2024
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  • Updated Tutorials Resources (markdown)

    @enjoy-digital enjoy-digital committed May 21, 2024
    67c2c95
  • Updated Tutorials Resources (markdown)

    @enjoy-digital enjoy-digital committed May 21, 2024
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  • Updated Tutorials Resources (markdown)

    @enjoy-digital enjoy-digital committed May 21, 2024
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  • Updated Tutorials Resources (markdown)

    @enjoy-digital enjoy-digital committed May 21, 2024
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  • Updated Projects (markdown)

    @enjoy-digital enjoy-digital committed Apr 19, 2024
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  • Updated JTAG GDB Debugging with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @trabucayre trabucayre committed Apr 15, 2024
    a049488
  • Updated JTAG GDB Debugging with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @trabucayre trabucayre committed Apr 12, 2024
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  • Updated JTAG GDB Debugging with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
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  • Updated JTAG GDB Debugging with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @trabucayre trabucayre committed Apr 12, 2024
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  • Updated JTAG GDB Debugging with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @trabucayre trabucayre committed Apr 12, 2024
    8713905
  • fix arty onboard interface name

    @trabucayre trabucayre committed Apr 12, 2024
    3abb8af
  • Updated _Sidebar (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
    46e4313
  • Updated Reuse a (System)Verilog, VHDL, Amaranth, Spinal HDL, Chisel core (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
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  • Updated Reuse a (System)Verilog, VHDL, (n)Migen, Spinal HDL, Chisel core (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
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  • Updated _Sidebar (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
    1b06872
  • Updated Use GDB with VexRiscv CPU (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
    5f397ca
  • Updated _Sidebar (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
    220e397
  • Updated _Sidebar (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
    1774b9d
  • Updated Use GDB with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
    a6d0da2
  • Updated Use GDB with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
    3c9356c
  • Updated Use GDB with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
    87b9d9c
  • Updated Use GDB with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
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  • Updated Use GDB with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
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  • Updated Use GDB with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
    af2ec87
  • Created Use GDB with VexRiscv SMP NaxRiscv VexiiRiscv CPUs (markdown)

    @enjoy-digital enjoy-digital committed Apr 12, 2024
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