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ulx3s ecp5 soc not working when using Lattice Diamond #1965
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I tried using LiteScope as described on this page Use LiteScope To Debug A SoC I then tried just capturing the 25MHz clock. analyzer_signals was changed to:
This works for both trellis and Diamond. I will see if LiteScope can be used to monitor anything else when my project is built using Diamond. |
If I change from vexriscv to picorv32, the soft cpu works, and I get the bios prompt. I am using the Windows GUI version of Diamond. Edit build/radiona_ulx3s/gateware/radiona_ulx3s.lpf and add the follolwing lines:
Edit build/radiona_ulx3s/gateware/radiona_ulx3s.tcl and comment out each line after "prj_project save"
Create the Diamond project by running
If I repeat the above with: The Diamond "Place & Route Trace" report shows:
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Hi, One thing i noticed is that some synthesis tools aren't following 1 to 1 the verilog description when it is about ram block inferation (that include vivado or ISE if i remember well) Can you try with the cpu-variant lite instead ? (to workaround the xilinx behaviour i had to add verilog attributes to the array) |
Hi Dolu1990
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That is realy weird :/
Looking at that screen shot Which mean the CPU should have happily jumped to 0xb0 and at least try to fetch some. "Likely" a illegal instruction trap. Could you check for : Thanks ^^ |
I was incorrect when I said the VexRiscv cpu-variants lite and full had the same result as minimal. They have the same result only as in I don't get the bios prompt, but the bus activity is very different. This is a capture of the boot of a Litex SOC (VexRiscv CPU cpu-variant minimal) built using Diamond: This is a capture of the boot of a Litex SOC (VexRiscv CPU cpu-variant lite) built using trellis: This is a capture of the boot of a Litex SOC (VexRiscv CPU cpu-variant lite) built using Diamond: After a short time, the Litex SOC (VexRiscv CPU cpu-variant lite) built using Diamond appears to lockup: I have attached the LiteScope boot capture files for the cpu-variant lite when built using Diamond and trellis. |
The VexRiscv CPU cpu-variant minimal trace (the first one) is quite interresting as we can see the decoding exception fireing again and again. I don't know much about Diamond, do you ? |
I have only recently started looking at Diamond. I will look into simulation with Diamond. |
If I perform the following steps, everything builds ok using trellis, and I get the BIOS prompt.
If I try using diamond 3.13, it builds without errors, but I don't get the BIOS prompt
If you are using the jtag module, you need to make some other changes as discussed here and here
litex/litex/soc/cores/jtag.py
Line 382 in 10083f4
Change from p_INIT = 2
to p_init = 2
I also possibly found some .lpf configuration issues. If I open the generated project "build/radiona_ulx3s/gateware/radiona_ulx3s.ldf" in the Diamond GUI, it shows "CONFIG_IOVOLTAGE 2.5" in Global Preferences. I believe this should be 3.3. Adding the following to "build/radiona_ulx3s/gateware/radiona_ulx3s.lpf" fixes that and also sets the bank voltages:
SYSCONFIG CONFIG_IOVOLTAGE=3.3;
BANK 0 VCCIO 3.3 V;
BANK 1 VCCIO 3.3 V;
BANK 2 VCCIO 3.3 V;
BANK 3 VCCIO 3.3 V;
BANK 6 VCCIO 3.3 V;
BANK 7 VCCIO 3.3 V;
BANK 8 VCCIO 3.3 V;
Lattice Diamond 3.13 builds the project without errors, but I don't still don't get the BIOS prompt. There are a lot of warnings though. Most are along the lines of logic being pruned because no output depends on it. The ones I have checked seem valid.
The LED chaser is working though.
Any ideas where I should look next, and has anyone managed to build a LiteX project for the ulx3s with Lattice Diamond?
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