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Makefile
Makefile
 
 
Pipelining.md
Pipelining.md
 
 
README.md
README.md
 
 
dac_6581_cutoff.hex
dac_6581_cutoff.hex
 
 
dac_6581_envelope.hex
dac_6581_envelope.hex
 
 
dac_6581_waveform.hex
dac_6581_waveform.hex
 
 
flash.bat
flash.bat
 
 
flash.sh
flash.sh
 
 
i2c_master.v
i2c_master.v
 
 
i2s_dsp_mode.sv
i2s_dsp_mode.sv
 
 
ice40_init.sv
ice40_init.sv
 
 
muacm.v
muacm.v
 
 
muladd.sv
muladd.sv
 
 
redip_sid.pcf
redip_sid.pcf
 
 
redip_sid.sv
redip_sid.sv
 
 
sgtl5000_init.v
sgtl5000_init.v
 
 
sgtl5000_init_data.hex
sgtl5000_init_data.hex
 
 
sid_api.sv
sid_api.sv
 
 
sid_api_sim.cpp
sid_api_sim.cpp
 
 
sid_control.sv
sid_control.sv
 
 
sid_dac.sv
sid_dac.sv
 
 
sid_envelope.sv
sid_envelope.sv
 
 
sid_filter.sv
sid_filter.sv
 
 
sid_io.sv
sid_io.sv
 
 
sid_pkg.sv
sid_pkg.sv
 
 
sid_pot.sv
sid_pot.sv
 
 
sid_voice.sv
sid_voice.sv
 
 
sid_waveform.sv
sid_waveform.sv
 
 
sid_waveform_PST.svh
sid_waveform_PST.svh
 
 
sid_waveform_PS__6581.hex
sid_waveform_PS__6581.hex
 
 
sid_waveform_PS__8580.hex
sid_waveform_PS__8580.hex
 
 
sid_waveform_P_T_6581.hex
sid_waveform_P_T_6581.hex
 
 
sid_waveform_P_T_8580.hex
sid_waveform_P_T_8580.hex
 
 
sid_waveform__ST.svh
sid_waveform__ST.svh
 
 

README.md

reDIP SID Gateware

Description

The reDIP SID FPGA gateware provides high quality SID emulation for the reDIP SID hardware.

The gateware owes its existence to reSID, the SID internals documentation by Leandro "drfiemost" Nini and Dieter "ttlworks" Mueller, auxiliary code and guidance from Sylvain "tnt" Munaut, and a lot of work :-)

The gateware implements cycle accurate emulation of the SID digital logic, and quite a few SID analog peculiarities. In order to make reasonably accurate emulation of some of these fit in the iCE40UP5K FPGA, a few novelties have been invented:

  • Combined sawtooth/triangle and pulse/sawtooth/triangle waveforms without lookup tables.
  • MOS6581 waveform, envelope, and filter cutoff DAC emulation without lookup tables.
  • Parameterizable filter cutoff curves requiring only a single 16kbit lookup table.

Furthermore, FPGA resources are shared by pipelining and time-division multiplexing. This is in contrast to the real SID chip, where there was sufficient die area to simply repeat functional modules for each voice.

By default, a single MOS6581 chip is emulated. The gateware also implements MOS8580 emulation and simultaneous emulation of two chips, however runtime configuration of these features are not yet implemented.

Installation

The gateware may be installed on the reDIP SID hardware via USB using dfu-util:

  • Connect a USB cable to enter the bootloader. The green LED should start blinking.
  • Install the gateware with ./flash.sh (Linux / Mac OS) or flash.bat (Windows).
  • Disconnect USB. If the board is still powered, then press the user button to boot.

Depending on the previously installed gateware, in order to enter the bootloader it may be required to keep the user button pressed while powering up the board.

License

This gateware is part of reDIP SID, a MOS 6581/8580 SID FPGA emulation platform. Copyright (C) 2022 - 2023 Dag Lem <resid@nimrod.no>

The source describes Open Hardware and is licensed under the CERN-OHL-S v2.

You may redistribute and modify the source and make products using it under the terms of the CERN-OHL-S v2.

This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable conditions.

Source location: https://github.com/daglem/reDIP-SID