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The HLS code generated for LetNet5 example can pass HLS, but it failed block-level synthesis in vpl with AWS F1 VU9P FPGA target. Here is the error message (not enough RAM18)
===>The following messages were generated while Compiling (synthesis checkpoint) kernel/IP: cl_default_function_1_0 Log file: /heterocl/samples/lenet/aws/build_dir.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/prj/prj.runs/cl_default_function_1_0_synth_1/runme.log :
ERROR: [VPL 8-5834] Design needs 114204 RAMB18 which is more than device capacity of 4320ERROR: [VPL 17-69] Command failed: Vivado Synthesis failedERROR: [VPL 60-773] In '/heterocl/samples/lenet/aws/build_dir.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/runme.log', caught Tcl error: One or more synthesis runs failed during dynamic region dcp generation
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, One or more synthesis runs failed during dynamic region dcp generation
ERROR: [VPL 60-704] Integration error, run 'my_rm_synth_1' couldn't start because one or more of the prerequisite runs failedERROR: [VPL 60-704] Integration error, run 'cl_default_function_1_0_synth_1' failed, please look at the run log file '/heterocl/samples/lenet/aws/build_dir.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/prj/prj.runs/cl_default_function_1_0_synth_1/runme.log' for more informationERROR: [VPL 60-1328] Vpl run 'vpl' failedERROR: [VPL 60-806] Failed to finish platform linkerINFO: [v++ 60-1442] [16:45:33] Run run_link: Step vpl: FailedTime (s): cpu = 00:00:33 ; elapsed = 00:44:48 . Memory (MB): peak = 1682.480 ; gain = 0.000 ; free physical = 22426 ; free virtual = 208647ERROR: [v++ 60-661] v++ link run 'run_link' failedERROR: [v++ 60-626] Kernel link failed to completeERROR: [v++ 60-703] Failed to finish linkingINFO: [v++ 60-1653] Closing dispatch client.make: *** [build_dir.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/kernel.xclbin] Error 1
The HLS code generated for LetNet5 example can pass HLS, but it failed block-level synthesis in vpl with AWS F1 VU9P FPGA target. Here is the error message (not enough RAM18)
I am using the HLS code in the master repo: https://github.com/cornell-zhang/heterocl/blob/master/samples/lenet/vhls_code.cl. The HLS code seems to be directly generated from the HCL code, which is unoptimized.
I will insert and primitives into HCL code and try that again with AWS F1 target. Just opening this issue for bookkeeping purpose.
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