ckoegel / ece310_proj1 Public

ECE 310 Project 1. A Serial BCD adder in Verilog.

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
work		work
BCD_add_4digit.v		BCD_add_4digit.v
BCD_digit_add.v		BCD_digit_add.v
README.md		README.md
dff_lib.v		dff_lib.v
fa_cla.v		fa_cla.v
fa_cla_4bit.v		fa_cla_4bit.v
invalid_BCD.v		invalid_BCD.v
piso20.v		piso20.v
plus6.v		plus6.v
serial_bcd_alu.v		serial_bcd_alu.v
serial_bcd_alu_tb.v		serial_bcd_alu_tb.v
serial_bcd_alu_tb.wlf		serial_bcd_alu_tb.wlf
sipo33.v		sipo33.v
transcript		transcript
vsim.wlf		vsim.wlf